# US 2021/0344348 A1 · Self-tuning phase-locked loop (pll) circuit

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- Number: US 2021/0344348 A1
- Document ID: US20210344348A1
- Status: Published application
- Kind: A1
- Application number: 16/862,066
- Filed: 2020-04-29
- Published: 2021-11-04
- Earliest claimed: 2020-04-29
- Assignees: Analog Devices International Unlimited Company
- Applicants: Analog Devices International Unlimited Company
- Inventors: Wreeju BHAUMIK; Batna SURYANARAYANA; Dheeraj ARIMBOOR
- Web page: https://patentgrep.com/patent/US20210344348A1

## CPC

- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/0992: {comprising a counter or a frequency divider}
- H03L 7/0995: {the oscillator comprising a ring oscillator}
- H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)}
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Embodiments may relate to techniques or circuitry for the control of a clock signal by a phase-locked loop (PLL) circuit. The technique may include the identification of a first parameter related to a gain of a digitally controlled oscillator (DCO) and a second parameter related to a resolution of a time-to-digital converter (TDC). The technique may then include the identification of a third parameter related to filter coefficients of a loop filter of the PLL circuit based on the first and second parameter. The circuit may then output a clock signal based on the first, second, and third parameters. Other embodiments may be described or claimed.

## Claims

### Claim 1

A method of controlling a clock signal by a phase-locked loop (PLL) circuit, wherein the method comprises:
identifying, by the PLL circuit, a first parameter related to a gain of a digitally controlled oscillator (DCO) of the PLL circuit;
identifying, by the PLL circuit, a second parameter related to a resolution of a time-to-digital converter (TDC) of the PLL circuit;
setting coefficients of a loop filter of the PLL circuit to modify a loop gain of the PLL circuit based on the first parameter and the second parameter; and
outputting, by the PLL circuit, the clock signal, where the clock signal is based on the coefficients of the loop filter.

### Claim 2

(canceled)

### Claim 3 (depends on 1)

The method of claim 1, wherein the identifying the second parameter is based on provision of a test pulse to the TDC.

### Claim 4 (depends on 1)

The method of claim 1, wherein the method further comprises storing the coefficients of the loop filter in a memory that is communicatively coupled with the PLL circuit.

### Claim 5 (depends on 1)

The method of claim 1, wherein setting the coefficients of the loop filter includes identifying, by the PLL circuit, the coefficients of the loop filter in a memory that is communicatively coupled with the PLL circuit.

### Claim 6 (depends on 1)

The method of claim 1, wherein the setting the coefficients of the loop filter includes identifying, by the PLL circuit, the coefficients of the loop filter based on a look-up table.

### Claim 7

(canceled)

### Claim 8

A phase-locked loop (PLL) circuit, comprising:
a time-to-digital convertor (TDC);
a digitally controlled oscillator (DCO);
a filter; and
a controller, configured to:
identify a gain of the DCO,
identify a resolution of the TDC, and
set one or more coefficients of the filter to modify a loop gain of the PLL circuit based on the identified gain of the DCO and the identified resolution of the TDC, wherein the loop gain is proportional to each of the gain of the DCO and a function of the one or more coefficients of the filter, and inversely proportional to the resolution of the TDC, and
wherein the DCO is configured to provide an output clock signal based on a reference clock signal and the one or more coefficients.

### Claim 9

(canceled)

### Claim 10 (depends on 8)

The PLL circuit of claim 8, wherein the controller is configured to identify the gain of the DCO prior to the identification of the resolution of the TDC.

### Claim 11 (depends on 8)

The PLL circuit of claim 8, wherein the controller is configured to receive the output clock signal provided by the DCO.

### Claim 12 (depends on 11)

The PLL circuit of claim 11, wherein the controller is configured to iteratively identify the gain of the DCO based on the output clock signal provided by the DCO.

### Claim 13 (depends on 8)

The PLL circuit of claim 8, wherein the TDC is configured to dynamically adjust a phase of the output clock signal based on a divided output clock.

### Claim 14 (depends on 8)

The PLL circuit of claim 8, wherein the filter is a second-order filter.

### Claim 15

(canceled)

### Claim 16

An electronic device, comprising:
a reference clock signal generator to generate a reference clock signal; and
a phase-locked loop (PLL) circuit that includes:
a time-to-digital converter (TDC),
a digitally controlled oscillator (DCO),
a filter, and
a controller to set, based on a gain of a DCO and a resolution of the TDC, at least one coefficient of the filter to achieve a target loop gain, wherein the loop gain is proportional to each of the gain of the DCO and a function of the at least one coefficient of the filter, and inversely proportional to the resolution of the TDC, and
wherein the DCO is configured to generate a clock signal based on the reference clock signal and the at least one coefficient.

### Claim 17 (depends on 16)

The electronic device of claim 16, further comprising a storage communicatively coupled with the PLL circuit, wherein one or more of the gain of the DCO, the resolution of the TDC, and the at least one coefficient are based on a pre-stored value in the storage.

### Claim at position 18

18-19. (canceled)

### Claim 20 (depends on 16)

The electronic device of claim 16, wherein the controller is configured to identify the resolution of the TDC based on provision of a test pulse to the TDC.

### Claim 21 (depends on 1)

The method according to claim 1, wherein modifying the loop gain based on the first parameter and the second parameter includes setting the coefficients of the loop filter to compensate for variations in the gain of the DCO and the resolution of the TDC.

### Claim 22 (depends on 8)

The PLL circuit according to claim 8, wherein the controller is configured to set the one or more coefficients to compensate for variations in the gain of the DCO and the resolution of the TDC.

### Claim 23 (depends on 8)

The PLL circuit according to claim 8, wherein the controller is configured to set the one or more coefficients to reduce the loop gain based on the gain of the DCO and the resolution of the TDC.

### Claim 24 (depends on 8)

The method according to claim 8, wherein the controller is configured to set the one or more coefficients to increase the loop gain based on the gain of the DCO and the resolution of the TDC.

### Claim 25 (depends on 8)

The PLL circuit according to claim 8, wherein the controller is configured to set the one or more coefficients to modify the loop gain of the PLL circuit by modifying a transfer function of the filter.

### Claim 26 (depends on 16)

The electronic device according to claim 16, wherein the controller is configured to set the at least one coefficient to modify a transfer function of the filter based on the gain of the DCO and the resolution of the TDC.