# US 2021/0344346 A1 · Integrated circuit including back side conductive lines for clock signals

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0344346 A1
- Document ID: US20210344346A1
- Status: Published application
- Kind: A1
- Application number: 17/186,256
- Filed: 2021-02-26
- Published: 2021-11-04
- Earliest claimed: 2020-04-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kam-Tou SIO; Jiun-Wei LU
- Web page: https://patentgrep.com/patent/US20210344346A1

## CPC

- H03K 19/1774: {for global signals, e.g. clock, reset}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- H03K 19/17784: for supply voltage
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

## Claims

### Claim 1

An integrated circuit, comprising:
a first latch circuit and a second latch circuit, wherein the first latch circuit is configured to transmit a plurality of data signals to the second latch circuit through a plurality of first conductive lines disposed on a front side of the integrated circuit; and
a clock circuit configured to transmit a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through a plurality of second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the clock circuit comprises:
a first inverter configured to generate the first clock signal, wherein each transistor in the first inverter includes a first quantity of fin structures; and
a second inverter configured to generate the second clock signal, wherein each transistor in the second inverter includes a second quantity of fin structures,
wherein the first quantity and the second quantity are different from each other.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the plurality of second conductive lines comprise:
a first group of conductive lines disposed in a first layer on the back side of the integrated circuit; and
a second group of conductive lines disposed in a second layer on the back side of the integrated circuit, wherein the first layer is closer to the front side of the integrated circuit than the second layer.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, further comprising:
at least one first via coupled between at least one of the first group of conductive lines and at least one of the second group of conductive lines; and
at least one second via coupled between the at least one of the first group of conductive lines and at least one gate included in the first latch circuit.

### Claim 5 (depends on 3)

The integrated circuit of claim 3, further comprising:
a plurality of power rails disposed in the first layer, wherein the first group of conductive lines are interposed between the plurality of power rails.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, further comprising:
a plurality of first power rails, wherein the plurality of first power rails and the plurality of second conductive lines are disposed in a first layer on the back side of the integrated circuit,
wherein at least one of the plurality of first power rails includes a first portion extending in a first direction and a second portion extending in a second direction different from the first direction, wherein the at least one of the plurality of first power rails surrounds at least one of the plurality of second conductive lines in a layout view.

### Claim 7 (depends on 6)

The integrated circuit of claim 6, further comprising:
a plurality of second power rails extending in the second direction and separate from each other in the first direction; and
a plurality of vias coupled between the plurality of first power rails and the plurality of second power rails.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, further comprising:
a plurality of power rails disposed in a first layer on the back side of the integrated circuit, wherein at least one of the plurality of power rails is L-shaped,
wherein the plurality of power rails are configured to transmit a first supply voltage and a second supply voltage to the first latch circuit and the second latch circuit.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, further comprising:
a plurality of first power rails to a plurality of fourth power rails disposed in first to fourth layers on the back side of the integrated circuit,
wherein the plurality of first power rails to the plurality of fourth power rails are configured to transmit at least one supply voltage to the first latch circuit, the second latch circuit, and the clock circuit.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the plurality of second conductive lines comprise:
a first group of conductive lines disposed in the first layer and interposed between the plurality of first power rails in a layout view; and
a second group of conductive lines disposed in the second layer and interposed between the plurality of second power rails in the layout view.

### Claim 11

An integrated circuit, comprising:
a flip flop circuit including a first cell having a first cell height and a second cell having a second cell height, and comprising:
a first transistor in the first cell, comprising:
a first gate configured to receive a first signal from a first conductive line disposed on a front side of the integrated circuit; and
a first active region configured to transmit a first clock signal, according to the first signal, to a second conductive line in a first layer on a back side, opposite to the front side, of the integrated circuit;
a third conductive line disposed in a second layer, below the first layer, on the back side of the integrated circuit and coupled to the second conductive line; and
a second transistor in the second cell, comprising:
a second gate configured to receive the first clock signal through a fourth conductive line which is disposed in the first layer on the back side of the integrated circuit and coupled to the third conductive line; and
a second active region configured to transmit a second clock signal, according to the first clock signal, to a fifth conductive line in the first layer on the back side of the integrated circuit, wherein the second clock signal is generated by inverting the first clock signal.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the first cell height and the second cell height are different from each other.

### Claim 13 (depends on 11)

The integrated circuit of claim 11, further comprising:
a first power rail and a second power rail that are disposed in the first layer on the back side of the integrated circuit, wherein the first power rail is configured to couple a third active region included in the first transistor to a first supply voltage, and the second power rail is configured to couple a fourth active region included in the second transistor to the first supply voltage,
wherein the second conductive line is interposed between the first power rail and the second power rail.

### Claim 14 (depends on 13)

The integrated circuit of claim 13, further comprising:
a plurality of the flip flop circuits in a plurality of flip flop cells, wherein the plurality of the flip flop cells abut each other along a direction; and
a third power rail and a fourth power rail that are disposed in the second layer on the back side of the integrated circuit and pass through the plurality of the flip flop cells in the direction, wherein the third power rail and the fourth power rail are configured to couple, respectively, the first power rail and the second power rail to the first supply voltage.

### Claim 15 (depends on 11)

The integrated circuit of claim 11, wherein the third conductive line extends across the first cell to the second cell.

### Claim 16 (depends on 11)

The integrated circuit of claim 11, further comprising:
a third transistor in the first cell, comprising:
a third gate configured to receive the first clock signal through a sixth conductive line which is disposed in the first layer on the back side of the integrated circuit and coupled to the third conductive line.

### Claim 17

A method, comprising:
forming an active device operating as a scan flip flop circuit on a front side of an integrated circuit;
forming a plurality of first conductive lines extending in a first direction in a first layer on a back side of the integrated circuit to transmit a first clock signal and a second clock signal to the active device;
forming a plurality of second conductive lines in the first layer on the back side of the integrated circuit to transmit a first supply voltage and a second supply voltage to the active device, wherein the plurality of first conductive lines are interposed between the plurality of second conductive lines;
forming a plurality of third conductive lines extending in a second direction different from the first direction in a second layer on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the plurality of first conductive lines, wherein the first layer is disposed between the second layer and the front side of the integrated circuit; and
forming a plurality of fourth conductive lines extending parallel to the plurality of third conductive lines in the second layer on the back side of the integrated circuit to transmit the first supply voltage and the second supply voltage to the plurality of second conductive lines, wherein the plurality of third conductive lines are interposed between the plurality of fourth conductive lines.

### Claim 18 (depends on 17)

The method of claim 17, wherein at least one of the plurality of second conductive lines includes a first portion extending in the first direction and a second portion extending in the second direction.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
forming a plurality of fifth conductive lines extending in the first direction and a plurality of sixth conductive lines extending in the second direction in a third layer and a fourth layer, respectively, on the back side of the integrated circuit to transmit the first supply voltage and the second supply voltage to the plurality of fourth conductive lines.

### Claim 20 (depends on 19)

The method of claim 19, wherein the third layer is sandwiched between the second layer and the fourth layer.