# US 2021/0344344 A1 · No-enable setup clock gater based on pulse > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0344344 A1 - Document ID: US20210344344A1 - Status: Published application - Kind: A1 - Application number: 16/862,071 - Filed: 2020-04-29 - Published: 2021-11-04 - Earliest claimed: 2020-04-29 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Vivekanandan Venugopal; Shuyan Lei; Wenhao Li; Hemangi U. Gajjewar - Web page: https://patentgrep.com/patent/US20210344344A1 ## CPC - H03K 19/094: using field-effect transistors - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03K 17/284: in field effect transistor switches - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high. ## Claims ### Claim 1 A circuit configured to: receive an enable signal and a clock signal; generate a pulse signal based on the clock signal; cause an output node to attain a high voltage level during a pulse event when the enable signal is low; and cause the output node to attain a low voltage level during the pulse event when the enable signal is high. ### Claim 2 (depends on 1) The circuit as recited in claim 1, wherein the circuit comprises: a pull-up transistor; a first pull-down stack comprising a first pair of N-type transistors; and a first pull-up stack comprising a first pair of P-type transistors; wherein the circuit is configured to: receive the clock signal on a gate of the pull-up transistor; receive the enable signal and the pulse signal on gates of the first pair of N-type transistors of the first pull-down stack; receive the enable signal and an inverted pulse signal on gates of the first pair of P-type transistors of the first pull-up stack; cause, using the first pull-up stack, an output node to attain the high voltage level during the pulse event when the enable signal is low; and cause, using the first pull-down stack, the output node to attain the low voltage level during the pulse event when the enable signal is high. ### Claim 3 (depends on 2) The circuit as recited in claim 2, further comprising a second pull-up stack of a second pair of P-type transistors, wherein the circuit is configured to receive the pulse signal on a gate of a first P-type transistor of the second pair of P-type transistors of the second pull-up stack. ### Claim 4 (depends on 3) The circuit as recited in claim 3, wherein the second pull-up stack is configured to hold the output node at the high voltage level after the pulse event has ended until a clock transition is detected. ### Claim 5 (depends on 3) The circuit as recited in claim 3, wherein the second pull-up stack is arranged in parallel with the first pull-up stack. ### Claim 6 (depends on 2) The circuit as recited in claim 2, further comprising a second pull-down stack of three N-type transistors, wherein the circuit is configured to receive the inverted pulse signal on a gate of a first N-type transistor of the second pull-down stack. ### Claim 7 (depends on 6) The circuit as recited in claim 6, wherein the second pull-down stack is configured to hold the output node at the low voltage level after the pulse event has ended until a clock transition is detected. ### Claim 8 A method comprising: receiving an enable signal and a clock signal; generating a pulse signal based on the clock signal; causing an output node to attain a high voltage level during a pulse event when the enable signal is low; and causing the output node to attain a low voltage level during the pulse event when the enable signal is high. ### Claim 9 (depends on 8) The method as recited in claim 8, further comprising: receiving the clock signal on a gate of a pull-up transistor; receiving the enable signal and the pulse signal on gates of a first pair of N-type transistors of a first pull-down stack; receiving the enable signal and an inverted pulse signal on gates of a first pair of P-type transistors of a first pull-up stack; causing, using the first pull-up stack, the output node to attain the high voltage level during the pulse event when the enable signal is low; and causing, using the first pull-down stack, the output node to attain the low voltage level during the pulse event when the enable signal is high. ### Claim 10 (depends on 9) The method as recited in claim 9, further comprising receiving the pulse signal on a gate of a first P-type transistor of a second pair of P-type transistors of a second pull-up stack. ### Claim 11 (depends on 10) The method as recited in claim 10, further comprising holding, by the second pull-up stack, the output node at the high voltage level after the pulse event has ended until a clock transition is detected. ### Claim 12 (depends on 10) The method as recited in claim 10, wherein the second pull-up stack is arranged in parallel with the first pull-up stack. ### Claim 13 (depends on 9) The method as recited in claim 9, further comprising receiving the inverted pulse signal on a gate of a first N-type transistor of a second pull-down stack. ### Claim 14 (depends on 13) The method as recited in claim 13, further comprising holding, by the second pull-down stack, the output node at the low voltage level after the pulse event has ended until a clock transition is detected. ### Claim 15 A system comprising: a pulse generator circuit configured to generate a pulse signal based on a clock signal; and a clock-gating circuit configured to: receive an enable signal and the clock signal; cause an output node to attain a high voltage level during a pulse event when the enable signal is low; and cause the output node to attain a low voltage level during the pulse event when the enable signal is high. ### Claim 16 (depends on 15) The system as recited in claim 15, wherein the clock-gating circuit is further configured to: receive the clock signal on a gate of a pull-up transistor; receive the enable signal and the pulse signal on gates of a first pair of N-type transistors of a first pull-down stack; receive the enable signal and an inverted pulse signal on gates of a first pair of P-type transistors of a first pull-up stack; cause, using the first pull-up stack, the output node to attain the high voltage level during the pulse event when the enable signal is low; and cause, using the first pull-down stack, the output node to attain the low voltage level during the high pulse event when the enable signal is high. ### Claim 17 (depends on 16) The system as recited in claim 16, wherein the clock-gating circuit further comprises a second pull-up stack of a second pair of P-type transistors, wherein the clock-gating circuit is configured to receive the pulse signal on a gate of a first P-type transistor of the second pair of P-type transistors of the second pull-up stack. ### Claim 18 (depends on 17) The system as recited in claim 17, wherein the second pull-up stack is configured to hold the output node at the high voltage level after the pulse event has ended until a clock transition is detected. ### Claim 19 (depends on 17) The system as recited in claim 17, wherein the second pull-up stack is arranged in parallel with the first pull-up stack. ### Claim 20 (depends on 16) The system as recited in claim 16, wherein the clock-gating circuit further comprises a second pull-down stack of three N-type transistors, wherein the clock-gating circuit is configured to receive the inverted pulse signal on a gate of a first N-type transistor of the second pull-down stack.