# US 2021/0344333 A1 · Control Circuit and Sensor Device

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- Number: US 2021/0344333 A1
- Document ID: US20210344333A1
- Status: Published application
- Kind: A1
- Application number: 17/286,243
- Filed: 2019-09-13
- Published: 2021-11-04
- Earliest claimed: 2018-10-18
- Assignees: Hitachi Astemo, Ltd.
- Applicants: Hitachi Astemo, Ltd.
- Inventors: Akeo SATOH; Akira KOTABE; Tatsuo NAKAGAWA
- Web page: https://patentgrep.com/patent/US20210344333A1

## CPC

- G01F 25/10: of flowmeters
- H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08)
- H03K 17/6872: {using complementary field-effect transistors}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- G01F: MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

To prevent an output of an intermediate potential by suppressing sneaking of a current from a signal line to a power line at the time of disconnection of a power supply. A control circuit which receives a power supply voltage from a power line L11 and outputs an output signal to a signal line L12 includes: a load R11 which is provided between the power line and the signal line; a first transistor P11 which is provided between the load and the signal line; a second transistor P12 which is provided between a well of the first transistor and the power line; and a gate control circuit 15 which connects a gate terminal of the first transistor and a gate terminal of the second transistor to the signal line and turns off the first transistor and the second transistor, at the time of disconnection of a power supply.

## Claims

### Claim 1

A control circuit which receives a power supply voltage from a power line and outputs an output signal to a signal line, comprising:
a load which is provided between the power line and the signal line;
a first transistor which is provided between the load and the signal line or between the power line and the load;
a second transistor which is provided between a well of the first transistor and the power line; and
a gate control circuit which connects a gate terminal of the first transistor and a gate terminal of the second transistor to the signal line and turns off the first transistor and the second transistor, at the time of disconnection of a power supply.

### Claim 2 (depends on 1)

The control circuit according to claim 1, wherein the gate control circuit turns on the first transistor by connecting the gate terminal of the first transistor and the gate terminal of the second transistor to a ground and making a well potential of the first transistor become a power supply potential via the second transistor, at the time of a normal operation.

### Claim 3 (depends on 1)

The control circuit according to claim 1, wherein the first transistor is a first P-channel metal oxide semiconductor (PMOS) transistor,
the second transistor is a second PMOS transistor,
the gate control circuit includes:
a first element which is provided between a connection point between a gate terminal of the first PMOS transistor and a gate terminal of the second PMOS transistor and a ground; and
a second element which is provided between the connection point between the gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor and the signal line, and
the gate control circuit connects the gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor to the ground via the first element at the time of a normal operation and connects the gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor to the signal line via the second element at the time of the disconnection of the power supply.

### Claim 4 (depends on 3)

The control circuit according to claim 3, wherein the first element is an N-channel metal oxide semiconductor (NMOS) transistor and the second element is a third PMOS transistor,
a gate terminal of the NMOS transistor is connected to the power line, and
a gate terminal of the third PMOS transistor is connected to the power line.

### Claim 5 (depends on 4)

The control circuit according to claim 4, wherein one input/output terminal of the second PMOS transistor is connected to the power line, and the other input/output terminal of the second PMOS transistor is connected to a well of the first PMOS transistor, a well of the second PMOS transistor, and a well of the third PMOS transistor.

### Claim 6 (depends on 5)

The control circuit according to claim 5, further comprising a fourth PMOS transistor which is provided between a connection point between the well of the first PMOS transistor and the well of the second PMOS transistor and the signal line,
wherein a gate terminal of the fourth PMOS transistor is connected to the power line.

### Claim 7 (depends on 6)

The control circuit according to claim 6, wherein one input/output terminal of the fourth PMOS transistor is connected to the well of the first PMOS transistor, the well of the second PMOS transistor, the well of the third PMOS transistor, and a well of the fourth PMOS transistor, and the other input/output terminal of the fourth PMOS transistor is connected to the signal line.

### Claim 8 (depends on 7)

The control circuit according to claim 7, wherein any one of the second PMOS transistor and the fourth PMOS transistor is replaced with a resistor.

### Claim 9 (depends on 3)

The control circuit according to claim 3, wherein the first element is a resistor, the second element is a third PMOS transistor, and a gate terminal of the third PMOS transistor is connected to the power line.

### Claim 10 (depends on 3)

The control circuit according to claim 3, wherein the first element is an NMOS transistor, the second element is a resistor, and a gate terminal of the NMOS transistor is connected to the power line.

### Claim 11 (depends on 1)

The control circuit according to claim 1, wherein the load is composed of a resistor or a transistor.

### Claim 12 (depends on 1)

A sensor device comprising:
the control circuit according to claim 1; and
a detection circuit which outputs a control signal according to a physical quantity to the control circuit.