# US 2021/0344330 A1 · Level conversion device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0344330 A1 - Document ID: US20210344330A1 - Status: Published application - Kind: A1 - Application number: 17/373,668 - Filed: 2021-07-12 - Published: 2021-11-04 - Earliest claimed: 2015-11-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Yu-Lun OU; Wei-Chih HSIEH; Shang-Chih HSIEH - Web page: https://patentgrep.com/patent/US20210344330A1 ## CPC - H03K 3/356: Bistable circuits - H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A device is disclosed and includes a first transistor, a second transistor, and a first current limiter. First terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors receive a first input signal. A first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal. A third output signal at the output terminal has a logic value different from that of the first input signal. ## Claims ### Claim 1 A device, comprising: a first transistor and a second transistor, wherein first terminals of the first and second transistors are coupled to an output terminal, and gate terminals of the first and second transistors are configured to receive a first input signal; and a first current limiter, wherein a first terminal of the first current limiter is coupled to a second terminal of the first transistor to output a first output signal, and a second terminal of the first current limiter is coupled to a second terminal of the second transistor to output a second output signal; wherein a third output signal at the output terminal has a logic value different from that of the first input signal. ### Claim 2 (depends on 1) The device of claim 1, wherein the first current limiter comprises: a third transistor having a first terminal as the first terminal of the first current limiter and a second terminal as the second terminal of the first current limiter; wherein the first output signal and the second output signal have a different logic value. ### Claim 3 (depends on 2) The device of claim 2, further comprising: a fourth transistor coupled between the first terminal of the first current limiter and a first voltage terminal, and configured to transmit a first current to the first current limiter; a fifth transistor coupled between the second terminal of the first current limiter and a second voltage terminal different from the first voltage terminal, and configured to transmit a second current associated with the first current to the second voltage terminal in response to the first input signal; a second current limiter having a control terminal coupled to a gate terminal of the fourth transistor; a sixth transistor coupled between the first voltage terminal and a first terminal of the second current limiter, and configured to transmit a third current in response to a signal received at the second terminal of the first current limiter; and a seventh transistor coupled between a second terminal of the second current limiter and the second voltage terminal, wherein a gate terminal of the seventh transistor is configured to receive a second input signal inverted from the first input signal. ### Claim 4 (depends on 1) The device of claim 1, further comprising: a third transistor coupled between the first terminal of the first current limiter and a first voltage terminal providing a first supply voltage; a fourth transistor coupled between the second terminal of the first current limiter and a second voltage terminal different from the first voltage terminal, wherein a gate terminal of the fourth transistor is configured to receive the first input signal; a fifth transistor having a first terminal and a gate terminal that are coupled to a gate terminal of the third transistor; an input signal generator configured to operate with a second supply voltage to generate a second input signal inverted from the first input signal; and a sixth transistor coupled between the first terminal of the fifth transistor and the second voltage terminal, wherein a gate terminal of the sixth transistor is configured to receive the second input signal; wherein the first supply voltage and the second supply voltage have different voltage levels. ### Claim 5 (depends on 1) The device of claim 1, further comprising: a third transistor coupled between the first terminal of the first current limiter and a first voltage terminal; a fourth transistor coupled to the second terminal of the first current limiter, wherein a gate terminal of the fourth transistor is configured to receive the first input signal; and a fifth transistor coupled between the fourth transistor and a second voltage terminal different from the first voltage terminal, and configured to transmit a current received from the fourth transistor to the second voltage terminal in response to an enable signal received at a gate terminal of the fifth transistor. ### Claim 6 (depends on 1) The device of claim 1, further comprising: a third transistor having a first terminal coupled to a first voltage terminal providing a first supply voltage; and a fourth transistor coupled between a second terminal of the third transistor and the first terminal of the first current limiter; wherein the third transistor is configured to be turned on, in response to an enable signal received at a gate terminal of the third transistor, to transmit the first supply voltage to the fourth transistor. ### Claim 7 (depends on 6) The device of claim 6, further comprising: a fifth transistor having a first terminal coupled to the second terminal of the third transistor and a gate terminal coupled to the second terminal of the first current limiter; a second current limiter having a control terminal coupled to a gate terminal of the fourth transistor and a first terminal coupled to a second terminal of the fifth transistor; and a sixth transistor coupled between a second terminal of the second current limiter and a second voltage terminal. ### Claim 8 (depends on 1) The device of claim 1, further comprising: an output stage configured to adjust a voltage swing of the third output signal. ### Claim 9 (depends on 1) The device of claim 1, further comprising: a third transistor coupled between the first terminal of the first current limiter and a first voltage terminal; and a fourth transistor having a first terminal coupled to a gate of the third transistor, a second terminal coupled a second voltage terminal different from the first voltage terminal, and a gate terminal configured to receive a second input signal; wherein the second input signal and one of the first output signal and the second output signal have different logic values. ### Claim 10 A device, comprising: a level shifter, comprising a first transistor and a second transistor, wherein a gate terminal of the first transistor is configured to receive a first input signal, and a gate terminal of the second transistor is configured to receive a second input signal having a logic value different from that of the first input signal; a third transistor having a first terminal coupled to a first output terminal of the level shifter to receive a first output signal and a gate terminal to receive the second input signal; and a fourth transistor having a first terminal coupled to a second output terminal, different from the first output terminal, of the level shifter to receive a second output signal and a gate terminal configured to receive the second input signal; wherein the first output signal and the second output signal have logic values different from each other. ### Claim 11 (depends on 10) The device of claim 10, wherein a second terminal of the third transistor is coupled to a second terminal of the fourth transistor. ### Claim 12 (depends on 10) The device of claim 10, wherein a second terminal of the third transistor and a second terminal of the fourth transistor are coupled together at an output node configured to output a third output signal; wherein a logic value of the third output signal is different from at least one of the first and second output signals. ### Claim 13 (depends on 10) The device of claim 10, wherein the level shifter further comprises: a fifth transistor coupled between the first and second output terminals of the level shifter, and configured to provide a threshold voltage between the first and second output terminals of the level shifter in order to enable the level shifter. ### Claim 14 (depends on 10) The device of claim 10, further comprising: a first inverter configured to generate the first input signal according to the second input signal; and a second inverter coupled to a second terminal of the third transistor and a second terminal of the fourth transistor, and configured to invert the first output signal or the second output signal to generate a third output signal. ### Claim 15 (depends on 10) The device of claim 10, further comprising: a fifth transistor coupled between a supply voltage terminal and second terminals of the first and second transistors, wherein a gate terminal of the fifth transistor is configured to receive an enable signal in order to enable the level shifter. ### Claim 16 (depends on 10) The device of claim 10, further comprising: an output stage coupled to second terminals of the third and fourth transistors, and configured to generate a third output signal, wherein a logic value of the third output signal is the same as, in response to the second input signal, a logic value of the first output signal or of the second output signal. ### Claim 17 A method, comprising: in response to a first input signal having a first logic level, generating, by a level shifter, a first output signal at a first output terminal of the level shifter; in response to the first input signal having a second logic level, generating, by the level shifter, a second output signal at a second output terminal of the level shifter; receiving, by a selector, the first output signal at a first input terminal of the selector and the second output signal at a second input terminal of the selector; and selecting, by the selector, the first output signal or the second output signal as a selected signal to be output to an output stage in response to the first input signal received at both of a third input terminal of the selector and a fourth input terminal of the selector, wherein the first to fourth terminals of the selector are different from each other. ### Claim 18 (depends on 17) The method of claim 17, further comprising: controlling, by a second input signal inverted from the first input signal, the level shifter to generate a current flowing between the first and second output terminals of the level shifter. ### Claim 19 (depends on 17) The method of claim 17, wherein the selected signal and one of the first and second output signals have different logic values. ### Claim 20 (depends on 17) The method of claim 17, wherein the third input terminal of the selector is a gate terminal of a first transistor in the selector, and the fourth input terminal of the selector is a gate terminal of a second transistor in the selector.