# US 2021/0344329 A1 · Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Power Savings

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- Number: US 2021/0344329 A1
- Document ID: US20210344329A1
- Status: Published application
- Kind: A1
- Application number: 17/327,365
- Filed: 2021-05-21
- Published: 2021-11-04
- Earliest claimed: 2020-05-04
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Vivekanandan Venugopal; Ajay Bhatia; Qi Ye
- Web page: https://patentgrep.com/patent/US20210344329A1

## CPC

- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H03K 3/037: Bistable circuits
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A circuit comprising:
a pair of cross-coupled inverters enabled by a pair of pull-up transistors, wherein sources of the pair of pull-up transistors are coupled to a supply voltage at a first voltage level;
one or more clock-gated P-type transistors coupled between drains of the pair of pull-up transistors, wherein gates of the one or more clock-gated P-type transistors are coupled to a clock signal, wherein a clock logic high level is equal to a second voltage level less than the first voltage level; and
a pair of clock-gated N-type transistors coupled in parallel to state nodes of the pair of cross-coupled inverters.

### Claim 22 (depends on 21)

The circuit as recited in claim 21, wherein:
a gate of a first pull-down transistor of the pair of pull-down transistors is configured to receive an input signal;
a gate of a second pull-down transistor of the pair of pull-down transistors is configured to receive an inverse of the input signal; and
a data logic high level of the input signal is equal to the first voltage level.

### Claim 23 (depends on 21)

The circuit as recited in claim 21, wherein when the clock signal is at the clock logic high level, the one or more clock-gated P-type transistors are configured to counteract the pair of clock-gated N-type transistors to cause one of the state nodes to reach the first voltage level.

### Claim 24 (depends on 21)

The circuit as recited in claim 21, wherein:
a drain of each transistor of the pair of clock-gated N-type transistors is coupled to a corresponding state node of the pair of cross-coupled inverters; and
a source of each transistor of the pair of clock-gated N-type transistors is coupled to a drain of a corresponding transistor of a pair of pull-down transistors.

### Claim 25 (depends on 21)

The circuit as recited in claim 21, wherein:
a source of a first P-type transistor of the one or more clock-gated P-type transistors is coupled to a drain of a first transistor of the pair of pull-up transistors;
a drain of the first P-type transistor is coupled to a drain of a second P-type transistor of the one or more clock-gated P-type transistors; and
a source of the second P-type transistor is coupled to a drain of a second transistor of the pair of pull-up transistors.

### Claim 26 (depends on 21)

The circuit as recited in claim 21, wherein:
a source of each of a first P-type transistor and a second P-type transistor of the one or more clock-gated P-type transistors is coupled to the supply voltage at the first voltage level;
a drain of the first P-type transistor is coupled to a source of a third P-type transistor;
a drain of the second P-type transistor is coupled to a source of a fourth P-type transistor; and
a gate of each of the third P-type transistor and the fourth P-type transistor is coupled to a logic low level.

### Claim 27 (depends on 26)

The circuit as recited in claim 26, wherein:
one or more P-type transistors with a gate coupled to a logic low level are connected in series between the drain of the third P-type transistor and a drain of a first transistor of the pair of pull-up transistors; and
one or more P-type transistors with a gate coupled to a logic low level are connected in series between the drain of the fourth P-type transistor and a drain of a second transistor of the pair of pull-up transistors.

### Claim 28

A method comprising:
supplying a pair of pull-up transistors with a supply voltage at a first voltage level;
enabling, by the pair of pull-up transistors, a pair of cross-coupled inverters;
receiving a clock signal at gates of one or more clock-gated P-type transistors coupled between drains of the pair of pull-up transistors, wherein a clock logic high level is equal to a second voltage level less than the first voltage level; and
receiving the clock signal at gates of a pair of clock-gated N-type transistors coupled in parallel to state nodes of the pair of cross-coupled inverters.

### Claim 29 (depends on 28)

The method as recited in claim 28, further comprising:
receiving an input signal by a gate of a first pull-down transistor of the pair of pull-down transistors; and
receiving an inverse of the input signal by a gate of a second pull-down transistor of the pair of pull-down transistors is configured to, wherein a data logic high level of the input signal is equal to the first voltage level.

### Claim 30 (depends on 28)

The method as recited in claim 28, further comprising counteracting, by the one or more clock-gated P-type transistors, the pair of clock-gated N-type transistors to cause one of the state nodes to reach the first voltage level when the clock signal is at the clock logic high level.

### Claim 31 (depends on 28)

The method as recited in claim 28, wherein:
a drain of each transistor of the pair of clock-gated N-type transistors is coupled to a corresponding state node of the pair of cross-coupled inverters; and
a source of each transistor of the pair of clock-gated N-type transistors is coupled to a drain of a corresponding transistor of a pair of pull-down transistors.

### Claim 32 (depends on 28)

The method as recited in claim 28, wherein:
a source of a first P-type transistor of the one or more clock-gated P-type transistors is coupled to a drain of a first transistor of the pair of pull-up transistors;
a drain of the first P-type transistor is coupled to a drain of a second P-type transistor of the one or more clock-gated P-type transistors; and
a source of the second P-type transistor is coupled to a drain of a second transistor of the pair of pull-up transistors.

### Claim 33 (depends on 28)

The method as recited in claim 28, wherein:
a source of each of a first P-type transistor and a second P-type transistor of the one or more clock-gated P-type transistors is coupled to the supply voltage at the first voltage level;
a drain of the first P-type transistor is coupled to a source of a third P-type transistor;
a drain of the second P-type transistor is coupled to a source of a fourth P-type transistor; and
a gate of each of the third P-type transistor and the fourth P-type transistor is coupled to a logic low level.

### Claim 34 (depends on 33)

The method as recited in claim 33, wherein:
one or more P-type transistors with a gate coupled to a logic low level are connected in series between the drain of the third P-type transistor and a drain of a first transistor of the pair of pull-up transistors; and
one or more P-type transistors with a gate coupled to a logic low level are connected in series between the drain of the fourth P-type transistor and a drain of a second transistor of the pair of pull-up transistors.

### Claim 35

A system comprising:
a clock generator circuit; and
logic circuitry comprising:
a pair of cross-coupled inverters enabled by a pair of pull-up transistors, wherein sources of the pair of pull-up transistors are coupled to a supply voltage at a first voltage level;
one or more clock-gated P-type transistors coupled between drains of the pair of pull-up transistors, wherein gates of the one or more clock-gated P-type transistors are coupled to a clock signal, wherein a clock logic high level is equal to a second voltage level less than the first voltage level; and
a pair of clock-gated N-type transistors coupled in parallel to state nodes of the pair of cross-coupled inverters.

### Claim 36 (depends on 35)

The system as recited in claim 35, wherein:
a gate of a first pull-down transistor of the pair of pull-down transistors is configured to receive an input signal;
a gate of a second pull-down transistor of the pair of pull-down transistors is configured to receive an inverse of the input signal; and
a data logic high level of the input signal is equal to the first voltage level.

### Claim 37 (depends on 35)

The system as recited in claim 35, wherein when the clock signal is at the clock logic high level, the one or more clock-gated P-type transistors are configured to counteract the pair of clock-gated N-type transistors to cause one of the state nodes to reach the first voltage level.

### Claim 38 (depends on 35)

The system as recited in claim 35, wherein:
a source of a first P-type transistor of the one or more clock-gated P-type transistors is coupled to a drain of a first transistor of the pair of pull-up transistors;
a drain of the first P-type transistor is coupled to a drain of a second P-type transistor of the one or more clock-gated P-type transistors; and
a source of the second P-type transistor is coupled to a drain of a second transistor of the pair of pull-up transistors.

### Claim 39 (depends on 35)

The system as recited in claim 35, wherein:
a source of each of a first P-type transistor and a second P-type transistor of the one or more clock-gated P-type transistors is coupled to the supply voltage at the first voltage level;
a drain of the first P-type transistor is coupled to a source of a third P-type transistor;
a drain of the second P-type transistor is coupled to a source of a fourth P-type transistor; and
a gate of each of the third P-type transistor and the fourth P-type transistor is coupled to a logic low level.

### Claim 40 (depends on 39)

The system as recited in claim 39, wherein:
one or more P-type transistors with a gate coupled to a logic low level are connected in series between the drain of the third P-type transistor and a drain of a first transistor of the pair of pull-up transistors; and
one or more P-type transistors with a gate coupled to a logic low level are connected in series between the drain of the fourth P-type transistor and a drain of a second transistor of the pair of pull-up transistors.