# US 2021/0344271 A1 · Error amplifier with accurate output clamp function

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- Number: US 2021/0344271 A1
- Document ID: US20210344271A1
- Status: Published application
- Kind: A1
- Application number: 16/865,398
- Filed: 2020-05-03
- Published: 2021-11-04
- Earliest claimed: 2020-05-03
- Assignees: Dongguan Changgong Microelectronics Ltd
- Applicants: Dongguan Changgong Microelectronics Ltd
- Inventors: WANGKE TAO
- Web page: https://patentgrep.com/patent/US20210344271A1

## CPC

- H02M 1/0003: {Details of control, feedback or regulation circuits}
- H02M 3/155: using semiconductor devices only
- H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M 3/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections}
- H02M 3/158: including plural semiconductor devices as final control devices for a single load
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

This present invention is an invented high-performance error amplifier concept and unique circuitry architecture for controller of switching mode power supply (SMPS). The invented error amplifier comprises a front-end buffer circuit, an embedded differential amplifier, an N-MOSFET based output driving stage and coupled passive RC network. The embedded error amplifier is constructed with two differential pair inputs and an output amplification stage. N-MOSFET output stage coupled to the output of the embedded differential amplifier enhances the load driving capability of proposed error amplifier. The clamp voltage can be configured by another passive network and an output stage with two current sources. This invention allows user to arbitrarily configure the clamp voltage level regardless of the error amplifier's bias voltage. In addition, the highly accurate clamp voltage level can be achieved without temperature drift issue.

## Claims

### Claim 1

A voltage regulator system, comprising:
a main circuit to draw power from its input terminal - Vin to produce a desired output voltage following commands from control circuit, wherein main circuit is coupled to a gate driver of a VR controller and provides power to load;
a control circuit to provide pulse width modulation (PWM) signal and MOSFET driving for the main circuit, wherein control circuit can be implemented as an independent component or integrated as part of the power device; and
a gate driver coupled between the main circuit and the control circuit to complete a feedback process, wherein the Gate driver may be embedded in either the VR controller or integrated as part of the main circuit.

### Claim 2 (depends on 1)

The system of claim 1, wherein the control circuit further comprises:
an output feedback voltage divider fed to the error amplifier;
an error amplifier coupled to an output feedback branch to complete error signal operation and handling, and the error amplifier's output signal to follow a fast PWM comparator, wherein appropriate RC network can be added to the error amplifier to obtain needed poles and zeros for a desired compensation effectiveness of VR control loop, and the invented error amplifier can be used to achieve better voltage regulation performance, such as low DC error, high bandwidth and faster response;
a fast PWM comparator to receive the error amplifier output and an artificial ramp signal to compare with direct feedback signal to generate PWM signal, which is coupled to an ON timer;
an ON timer coupled to the fast PWM comparator output to determine a PWM signal sequence and width; and
a gate driver as a bridge coupled between the main circuit and control circuit to receive PWM signal and drive MOSFET devices of the main circuit.

### Claim 3 (depends on 2)

The system of claim 2, wherein the error amplifier of the control circuit further comprises:
a front-end buffer circuit;
an embedded error amplifier with two differential pair inputs and an output amplification stage;
a first feedback network that determines the high-end clamp voltage and the low-end clamp voltage;
a second feedback network that determines the main pole; and
an N-Channel MOSFET based output driving stage which output terminal is connected to two current sources: a RC feedback compensation network and a resistor feedback voltage divider network, and wherein the gate of the N-MOSFET is connected the output of the embedded error amplifier.

### Claim 4 (depends on 3)

The system of claim 3, wherein the front-end buffer circuit of the error amplifier further comprises:
a current mirror circuit formed by two P-Channel MOSFETs;
a differential pair formed by two N-Channel MOSFETs and a bias current source, wherein the first N-MOSFET's gate is connected to the IN terminal and the drain is connected to the first P-MOSFET's drain in the current mirror circuit, and the second N-MOSFET's gate is connected to the OUT terminal and the drain is connected to the second P-MOSFET's drain in the current mirror circuit;
an output stage based on a P-Channel MOSFET voltage follower to increase output driving capability, wherein this P-MOSFET's gate is connected to the second N-MOSFET's drain in the current mirror circuit, and the source is connected to the VCC terminal and the drain is connected to the output terminal;
a capacitor is connected between the gate and the source terminal of the P-MOSFET to stabilize the output; and
a pull-down resistor connected to the drain terminal of P-MOSFET as the output terminal to determines output voltage scaling.

### Claim 5 (depends on 3)

The system of claim 3, wherein the embedded error amplifier circuit of the error amplifier further comprises:
a supply and a ground connected to the MOSFETs and current sources of the embedded error amplifier circuit;
a one or more differential pairs;
a current mirror circuit formed by two P-MOSFETs;
an output amplification stage formed by a pair of common base N-Channel MOSFETs; and
two current sources connected to output amplification stage.

### Claim 6 (depends on 5)

The system of claim 5, wherein the two differential pairs of the embedded error amplifier circuit further comprises:
four input terminals made of a first and second sets of inverting input terminals and noninverting inputs, wherein the input terminals are connected to the gates of P-MOSFETs respectively;
two reference current sources, wherein the current source draw current from the bias terminal to supply the source of both P-MOSFETs;
a first differential pair based on a pair of P-MOSFETs, wherein both the source terminals are connected to the first current source, and the gate of the first P-MOSFET in the first differential pair is connected to the first inverting input terminal and the gate of the second P-MOSFET is connected to the first noninverting input terminal;
a second differential pair based on a pair of P-MOSFETs, wherein both source terminals are connected to the second current source, and the gate of the first P-MOSFET in the second differential pair is connected to the second noninverting input terminal and the gate of the second P-MOSFET is connected to the second inverting input terminal.

### Claim 7 (depends on 5)

The system of claim 5, wherein the current mirror circuit of the embedded error amplifier circuit further comprises:
two P-MOSFETs, wherein the both sources of both P-MOSFETs are connected to the bias terminal, the gate of both P-MOSFETs are connected together and also to the first P-MOSFET's drain, and the drain of the second P-MOSFET is connected to the output terminal of the embedded error amplifier.

### Claim 8 (depends on 5)

The system of claim 5, wherein the output amplification stage of the embedded error amplifier circuit further comprises two N-MOSFETs, wherein the gates of both the N-MOSFETs are tied together to an inside bias, and the drain terminal of the first N-MOSFET is connected to the first P-MOSFET's drain in the current mirror circuit and the drain terminal of the second N-MOSFET is connected to the second P-MOSFET's drain in the current mirror circuit; the source of the first N-MOSFET is connected to the drain of the differential pairs' P-MOSFETs, the gates of which are connected to the noninverting input terminals, and the source of the second N-MOSFET is connected the drain of the aforementioned differential pairs' P-MOSFETs, the gates of which are connected to the inverting input terminals.

### Claim 9 (depends on 3)

The system of claim 3, wherein the first feedback network of the embedded error amplifier circuit comprises:
a resistor connected to feedback terminal and the inverting input terminal of the embedded error amplifier; and
a capacitor connected to the inverting input terminal and output terminal of the embedded error amplifier, where determine major pole for a low pass filter effectiveness.

### Claim 10 (depends on 3)

The system of claim 3, wherein the second feedback network of the error amplifier circuit comprises:
a first resistor connected the output of the buffer and the second inverting input terminal of the embedded error amplifier; and
a second resistor connects the second inverting input terminal with the output of the error amplifier, and the second feedback network determines the high-end clamp voltage and the low-end clamp voltage.

### Claim 11 (depends on 3)

The system of claim 3, wherein the output amplification stage of the error amplifier circuit further comprises:
an N-MOSFET, wherein the N-Channel MOSFET gate is connected to the output terminal of the embedded amplifier and the two feedback networks, and the N-Channel MOSFET drain is connected to a current source, the source terminal of which as the output terminal is connected to one current source and this output stage is constructed in voltage follower structure to enhance load driving capability;
a first current source coupled to the supply to supply current bias to the drain of the N-MOSFET; and
a second current source connected to ground, wherein the terminal of the current source is connected to the node to tie two feedback network terminals and the output of the error amplifier.