# US 2021/0344266 A1 · Ultra-low-power mode control circuit for power converter

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- Number: US 2021/0344266 A1
- Document ID: US20210344266A1
- Status: Published application
- Kind: A1
- Application number: 16/968,594
- Filed: 2020-04-30
- Published: 2021-11-04
- Earliest claimed: 2019-05-23
- Assignees: Southeast University
- Applicants: Southeast University
- Inventors: Chao CHEN; Jun YANG; Xinning LIU
- Web page: https://patentgrep.com/patent/US20210344266A1

## CPC

- H02M 1/0032: {Control circuits allowing low power mode operation, e.g. in standby mode}
- H02M 1/0006: {Arrangements for supplying an adequate voltage to the control circuit of converters}
- H02M 1/0041: {Control circuits in which a clock signal is selectively enabled or disabled}
- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H03K 3/037: Bistable circuits
- H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H02M 3/1563: {without using an external clock (H02M3/158 takes precedence)}
- Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS

## Abstract

An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.

## Claims

### Claim 1

An ultra-low-power mode control circuit for a power converter, comprising:
a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first capacitor, a second capacitor, a first inverter and a second inverter;
wherein
a source of the first PMOS transistor is connected to a high-voltage power source, a gate of the first PMOS transistor is connected to a drain of the second PMOS transistor, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor;
a gate of the first NMOS transistor is connected to a mode selection switch, and a source of the first NMOS transistor is grounded;
a source of the second PMOS transistor is connected to the high-voltage power source, and a gate of the second PMOS transistor is connected to the drain of the first PMOS transistor;
a drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, a gate of the second NMOS transistor is connected to a drain of the fourth NMOS transistor, and a source of the second NMOS transistor is grounded;
a gate of the fourth NMOS transistor is connected to the mode selection switch, and a source of the fourth NMOS transistor is grounded;
a gate of the third NMOS transistor is grounded, a drain of the third NMOS transistor is connected to the mode selection switch, and a source of the third NMOS transistor is grounded;
a positive terminal of the first capacitor is connected to the mode selection switch, and a negative terminal of the first capacitor is grounded;
a positive terminal of the second capacitor is connected to the high-voltage power source, and a negative terminal of the second capacitor is connected to the drain of the fourth NMOS transistor;
a source of the third PMOS transistor is connected to the high-voltage power source, a gate of the third PMOS transistor is connected to the high-voltage power source, and a drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor;
a drain of the fifth NMOS transistor is connected to the drain of the second NMOS transistor, a gate of the fifth NMOS transistor is connected to a drain of the sixth NMOS transistor, and a source of the fifth NMOS transistor is grounded;
a gate of the sixth NMOS transistor is connected to the mode selection switch, and a source of the sixth NMOS transistor is grounded;
a drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor, a gate of the fourth PMOS transistor is connected to the mode selection switch, and a source of the fourth PMOS transistor is connected to a core voltage;
an input of the first inverter is connected to the drain of the second PMOS transistor, and an output of the first inverter is connected to an external clock enable signal; and
an input of the second inverter is connected to the drain of the first PMOS transistor, and an output of the second inverter is connected to a built-in clock enable signal.

### Claim 2 (depends on 1)

The ultra-low-power mode control circuit for the power converter according to claim 1, wherein, when a chip is powered on and a core voltage has not been established, the ultra-low-power mode control circuit starts a built-in clock of a power source to support operation of the power converter;
when the core voltage is established, the ultra-low-power mode control circuit determines whether to switch to an external clock according to a level of a mode selection signal; and
after the core voltage is powered down, the ultra-low-power mode control circuit automatically wakes up the built-in clock to work.