# US 2021/0344222 A1 · Charging an input capacitor of a load control device

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- Number: US 2021/0344222 A1
- Document ID: US20210344222A1
- Status: Published application
- Kind: A1
- Application number: 17/377,834
- Filed: 2021-07-16
- Published: 2021-11-04
- Earliest claimed: 2013-03-14
- Assignees: Lutron Technology Company LLC
- Applicants: Lutron Technology Company LLC
- Inventors: Mark Taipale; Matthew R. Blakeley; Johnathan P. Ross; Russell L. MacAdam
- Web page: https://patentgrep.com/patent/US20210344222A1

## CPC

- H02J 13/14: the power network being locally controlled, e.g. home energy management systems [HEMS]
- H02J 13/1313: {using pulsed signals}
- H05B 45/10: Controlling the intensity of the light
- H05B 47/10: Controlling the light source
- H05B 47/105: in response to determined parameters
- H05B 47/11: by determining the brightness or colour temperature of ambient light
- H05B 47/115: by determining the presence or movement of objects or living beings
- H05B 47/165: following a pre-assigned programmed sequence; Logic control [LC]
- H05B 47/18: via data-bus transmission
- H05B 47/185: via power line carrier transmission
- H05B 47/19: via wireless transmission
- H05B 47/1985: {Creation of lighting zones or scenes}
- H02J 2105/12: supplying households or buildings
- H05B 47/183: {using digital addressable lighting interface [DALI] communication protocols}
- H05B 47/196: {characterised by user interface arrangements}
- H05B 47/1965: {using handheld communication devices}
- H05B 47/198: {Grouping of control procedures or address assignation to light sources}
- Y02B 20/40: Control techniques providing energy savings, e.g. smart controller or presence detection
- Y02B 70/30: Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
- Y02B 90/20: Smart grids as enabling technology in buildings sector (smart grids supporting the management or operation of end-user stationary applications in general, or like technologies with no associated climate change mitigation effect Y04S20/00)
- Y04S 20/246: the system involving the remote operation of lamps or lighting equipment
- Y04S 40/121: using the power network as support for the transmission
- H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H05B: ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y04S: SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS

## Abstract

A load control device for controlling the amount of power delivered to an electrical load may include a rectifier circuit configured to receive a phase-control voltage and produce a rectified voltage. A power converter may be configured to receive the rectified voltage at an input and generate a bus voltage. An input capacitor may be coupled across the input of the power converter. The input capacitor may be adapted to charge when the magnitude of the phase control voltage is approximately zero volts. The power converter may be configured to operate in a boost mode, such that the magnitude of the bus voltage is greater than a peak magnitude of the input voltage. The power converter may be configured to operate in a buck mode to charge the input capacitor from the bus voltage when the magnitude of the phase-control voltage is approximately zero volts.

## Claims

### Claim 1

An electrical load control apparatus, comprising:
a controllably conductive device to receive an alternating current (AC) supply voltage; and
phase-control circuitry communicatively coupled to the memory circuitry and the controllably conductive device, the phase-control circuitry to:
selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a phase controlled alternating current (AC) output voltage;
generate a reference edge in a first half-cycle of the AC output voltage contemporaneous with a first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states; and
select one of a plurality of offset times to generate one of a corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with a second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states;
wherein each of the plurality of offset times corresponds to a different, unique, binary value.

### Claim 2 (depends on 1)

The electrical load control apparatus of claim 1:
wherein the phase-controlled AC voltage consists of a forward phase-control AC voltage;
wherein the controllably conductive device generates the reference edge contemporaneous with the first transition from the NON-CONDUCTIVE state to the CONDUCTIVE state; and
wherein the controllably conductive device generates the reference edge contemporaneous with the second transition from the NON-CONDUCTIVE state to the CONDUCTIVE state.

### Claim 3 (depends on 1)

The electrical load control apparatus of claim 1:
wherein the phase-controlled AC voltage consists of a reverse phase-control AC voltage;
wherein the controllably conductive device generates the reference edge contemporaneous with the first transition from the CONDUCTIVE state to the NON-CONDUCTIVE state; and
wherein the controllably conductive device generates the reference edge contemporaneous with the second transition from the CONDUCTIVE state to the NON-CONDUCTIVE state.

### Claim 4 (depends on 1)

The electrical load control apparatus of claim 1 wherein the plurality of offset times corresponds to 2n discrete offset times and the different, unique binary values correspond to 2n different, unique, binary sequences.

### Claim 5 (depends on 4)

The electrical load control apparatus of claim 4 wherein n=2.

### Claim 6 (depends on 5)

The electrical load control apparatus of claim 5, the control circuitry to:
generate a 20-bit data frame transmitted over 10 AC cycles.

### Claim 7 (depends on 6)

The electrical load control apparatus of claim 6 wherein to generate the 20-bit data frame, the control circuitry to further:
generate a 4-bit start sequence field;
generate a 4-bit channel mask field;
generate a 2-bit command field;
generate a 5-bit data field; and
generate a 5-bit error detect field.

### Claim 8

An electrical load control method, comprising:
selectively transitioning, by phase-control circuitry, a controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a phase controlled alternating current (AC) output voltage;
generating, by the phase-control circuitry, a reference edge in a first half-cycle of the AC output voltage contemporaneous with a first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states; and
selecting, by the phase-control circuitry, one of a plurality of offset times to generate one of a corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with a second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states;
wherein each of the plurality of offset times corresponds to a different, unique, binary value.

### Claim 9 (depends on 8)

The method of claim 8:
wherein selectively transitioning the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further comprises:
selectively transitioning, by the phase-control circuitry, the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a forward phase-control AC voltage;
wherein generating the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:
generating, by the phase-control circuitry, the reference edge contemporaneous with the first transition from the NON-CONDUCTIVE state to the CONDUCTIVE state; and
wherein generating one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:
generating, by the phase-control circuitry, the reference edge contemporaneous with the second transition from the NON-CONDUCTIVE state to the CONDUCTIVE state.

### Claim 10 (depends on 8)

The method of claim 8:
wherein selectively transitioning the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further comprises:
selectively transitioning, by the phase-control circuitry, the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a reverse phase-control AC voltage;
wherein generating the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:
generating, by the phase-control circuitry, the reference edge contemporaneous with the first transition from the CONDUCTIVE state to the NON-CONDUCTIVE state; and
wherein generating one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further comprises:
generating, by the phase-control circuitry, the reference edge contemporaneous with the second transition from CONDUCTIVE state to the NON-CONDUCTIVE state.

### Claim 11 (depends on 8)

The method of claim 8 wherein selecting one of the plurality of offset times to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage further comprises:
selecting, by the phase-control circuitry, one of 2n discrete offset times to generate a respective data edge at each of the 2n discrete offset times in the second half-cycle of the AC output voltage to provide 2n binary sequences, each corresponding to one of the 2n offset times.

### Claim 12 (depends on 11)

The method of claim 11 wherein selecting one of 2n discrete offset times to generate the respective data edge at each of the 2n discrete offset times in the second half-cycle of the AC output voltage to provide 2n binary sequences, each corresponding to one of the 2n offset times further comprises:
selecting, by the phase-control circuitry, one of 22 discrete offset times to generate a respective data edge at each of the 22 discrete offset times in the second half-cycle of the AC output voltage to provide 22 binary sequences, each corresponding to one of the 22 offset times.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
generating, by the phase-control circuitry, a 20-bit data frame transmitted over 10 AC cycles.

### Claim 14 (depends on 13)

The method of claim 13 wherein generating the 20-bit data frame transmitted over 10 AC cycles further comprises:
generating, by the phase-control circuitry, a 4-bit start sequence field;
generating, by the phase-control circuitry, a 4-bit channel mask field;
generating, by the phase-control circuitry, a 2-bit command field;
generating, by the phase-control circuitry, a 5-bit data field; and
generating, by the phase-control circuitry, a 5-bit error detect field.

### Claim 15

A non-transitory, machine-readable, storage device that includes instructions that, when executed by phase-control circuitry, causes the phase-control circuitry to:
selectively transition a controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a phase controlled alternating current (AC) output voltage;
generate a reference edge in a first half-cycle of the AC output voltage contemporaneous with a first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states; and
select one of a plurality of offset times to generate one of a corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with a second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states;
wherein each of the plurality of offset times corresponds to a different, unique, binary value.

### Claim 16 (depends on 15)

The non-transitory, machine-readable, storage device of claim 15:
wherein the instructions that cause the phase-control circuitry to selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further cause the phase-control circuitry to:
selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a forward phase-control AC voltage;
wherein the instructions that cause the phase-control circuitry to generate the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the phase-control circuitry to:
generate the reference edge contemporaneous with the first transition from the NON-CONDUCTIVE state to the CONDUCTIVE state; and
wherein the instructions that cause the phase-control circuitry to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the control circuitry to:
generate the reference edge contemporaneous with the second transition from the NON-CONDUCTIVE state to the CONDUCTIVE state.

### Claim 17 (depends on 15)

The non-transitory, machine-readable, storage device of claim 15:
wherein the instructions that cause the phase-control circuitry to selectively transition the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate the phase controlled alternating current (AC) output voltage further cause the phase-control circuitry to:
selectively transitioning, by the phase-control circuitry, the controllably conductive device between CONDUCTIVE and NON-CONDUCTIVE states to generate a reverse phase-control AC voltage;
wherein the instructions that cause the phase-control circuitry to generate the reference edge in the first half-cycle of the AC output voltage contemporaneous with the first transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the phase-control circuitry to:
generate the reference edge contemporaneous with the first transition from the CONDUCTIVE state to the NON-CONDUCTIVE state; and
wherein the instructions that cause the phase-control circuitry to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage contemporaneous with the second transition of the controllably conductive device between the CONDUCTIVE and NON-CONDUCTIVE states further cause the control circuitry to:
generate the reference edge contemporaneous with the second transition from CONDUCTIVE state to the NON-CONDUCTIVE state.

### Claim 18 (depends on 15)

The non-transitory, machine-readable, storage device of claim 15 wherein the instructions that cause the phase-control circuitry to select one of the plurality of offset times to generate one of the corresponding plurality of data edges in the second half-cycle of the AC output voltage further cause the phase-control circuitry to:
select one of 2n discrete offset times to generate a respective data edge at each of the 2n discrete offset times in the second half-cycle of the AC output voltage to provide 2n binary sequences, each corresponding to one of the 2n offset times.

### Claim 19 (depends on 18)

The non-transitory, machine-readable, storage device of claim 18 wherein the instructions that cause the phase-control circuitry to select one of 2n discrete offset times to generate the respective data edge at each of the 2n discrete offset times in the second half-cycle of the AC output voltage to provide 2n binary sequences, each corresponding to one of the 2n offset times further cause the phase-control circuitry to:
select one of 22 discrete offset times to generate a respective data edge at each of the 22 discrete offset times in the second half-cycle of the AC output voltage to provide 22 binary sequences, each corresponding to one of the 22 offset times.

### Claim 20 (depends on 19)

The non-transitory, machine-readable, storage device of claim 19 wherein the instructions further cause the phase-control circuitry to:
generate a 20-bit data frame transmitted over 10 AC cycles.

### Claim 21 (depends on 20)

The non-transitory, machine-readable, storage device of claim 20 wherein the instructions that cause the phase-control circuitry to generate the 20-bit data frame transmitted over 10 AC cycles further cause the phase-control circuitry to:
generate a 4-bit start sequence field;
generate a 4-bit channel mask field;
generate a 2-bit command field;
generate a 5-bit data field; and
generate a 5-bit error detect field.