# US 2021/0343786 A1 · Semiconductor device and method for fabricating the same

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- Number: US 2021/0343786 A1
- Document ID: US20210343786A1
- Status: Published application
- Kind: A1
- Application number: 16/882,783
- Filed: 2020-05-26
- Published: 2021-11-04
- Earliest claimed: 2020-04-30
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Hui-Lin Wang; Po-Kai Hsu; Jing-Yin Jhang; Yu-Ping Wang; Hung-Yueh Chen; Wei Chen
- Web page: https://patentgrep.com/patent/US20210343786A1

## CPC

- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 50/85: Materials of the active region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
forming a magnetic tunneling junction (MTJ) on a substrate;
forming a first inter-metal dielectric (IMD) layer around the MTJ;
forming a first metal interconnection adjacent to the MTJ;
forming a stop layer on the first IMD layer;
removing the stop layer to form an opening; and
forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

### Claim 2 (depends on 1)

The method of claim 1, wherein the substrate comprises a magnetic random access memory (MRAM) region and a logic region, the method comprising:
forming a second IMD layer on the substrate;
forming a second metal interconnection in the second IMD layer;
forming the MTJ on the second metal interconnection;
forming the first IMD layer around the MTJ;
forming the first metal interconnection on the MRAM region and a third metal interconnection on the logic region;
forming the stop layer on the MTJ, the first metal interconnection and the third metal interconnection;
forming the opening on the MRAM region; and
forming the channel layer in the opening.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a third IMD layer on the stop layer and the channel layer; and
forming a fourth metal interconnection in the third IMD layer to electrically connect the channel layer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising planarizing the channel layer before forming the third IMD layer.

### Claim 5 (depends on 2)

The method of claim 2, wherein the MTJ comprises:
a pinned layer on the second metal interconnection;
a barrier layer on the pinned layer; and
a free layer on the barrier layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the channel layer and the first metal interconnection comprise different materials.

### Claim 7 (depends on 1)

The method of claim 1, wherein the channel layer comprises metal.

### Claim 8

A semiconductor device, comprising:
a magnetic tunneling junction (MTJ) on a substrate;
a first inter-metal dielectric (IMD) layer around the MTJ;
a first metal interconnection adjacent to the MTJ; and
a channel layer on the first IMD layer to electrically connect the MTJ and the first metal interconnection.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising a second metal interconnection under the MTJ, wherein bottom surfaces of the first metal interconnection and the second metal interconnection are coplanar.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the MTJ comprises:
a pinned layer on the second metal interconnection;
a barrier layer on the pinned layer; and
a free layer on the barrier layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising a stop layer around the channel layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein top surfaces of the channel layer and the stop layer are coplanar.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the channel layer and the first metal interconnection comprise different materials.

### Claim 14 (depends on 8)

The semiconductor device of claim 8, wherein the channel layer comprises metal.

### Claim 15

A semiconductor device, comprising:
a first metal interconnection and a second metal interconnection on a substrate;
a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection;
a channel layer on the first IMD layer, the first metal interconnection, and the second metal interconnection; and
a magnetic tunneling junction (MTJ) on the channel layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the MTJ comprises:
a free layer on the channel layer;
a barrier layer on the free layer; and
a pinned layer on the barrier layer.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further comprising a stop layer around the channel layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein top surfaces of the channel layer and the stop layer are coplanar.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprising:
a cap layer on the channel layer and the stop layer and adjacent to the MTJ;
a second IMD layer around the cap layer; and
a third metal interconnection on the MTJ, the cap layer, and the second IMD layer.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the channel layer comprises metal.