# US 2021/0343718 A1 · Capacitor and forming method thereof, and dram and forming method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0343718 A1 - Document ID: US20210343718A1 - Status: Published application - Kind: A1 - Application number: 17/374,969 - Filed: 2021-07-13 - Published: 2021-11-04 - Earliest claimed: 2020-03-02 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Wenfeng WANG; Shuangshuang WU - Web page: https://patentgrep.com/patent/US20210343718A1 ## CPC - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/033: {the capacitor extending over the transistor} - H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching} - H10D 1/716: {having vertical extensions} - H10W 44/00: Electrical arrangements for controlling or matching impedance - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for forming a capacitor includes: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer. ## Claims ### Claim 1 A method for forming a capacitor, comprising: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole, in which the bottom electrode layer connects to the electric contact portion; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer on an inner surface and an outer surface of the bottom electrode layer and a surface of the supporting layer. ### Claim 2 (depends on 1) The method for forming a capacitor of claim 1, wherein the protective layer is formed by an atomic layer deposition process. ### Claim 3 (depends on 2) The method for forming a capacitor of claim 2, wherein a material of the protective layer is same as a material of the sacrificial layer. ### Claim 4 (depends on 3) The method for forming a capacitor of claim 3, wherein the material of the protective layer is silicon oxide. ### Claim 5 (depends on 1) The method for forming a capacitor of claim 1, wherein the thickness of the protective layer is 8 nm to 12 nm. ### Claim 6 (depends on 1) The method for forming a capacitor of claim 1, wherein a method for removing the sacrificial layer comprises: forming a hard mask layer on a surface of a top supporting layer; patterning the hard mask layer to form a patterned hard mask layer; by taking the patterned hard mask layer as a mask, etching the top supporting layer to form an etching window which exposes a top sacrificial layer; removing the top sacrificial layer along the etching window by a wet etching process; and sequentially etching a lower supporting layer and removing a lower sacrificial layer until all sacrificial layers are removed. ### Claim 7 (depends on 6) The method for forming a capacitor of claim 6, wherein the protective layer is removed while the top sacrificial layer is removed. ### Claim 8 (depends on 7) The method for forming a capacitor of claim 7, wherein in the wet etching process, an etching rate of the protective layer is smaller than an etching rate of the sacrificial layer. ### Claim 9 (depends on 6) The method for forming the capacitor according to claim 6, wherein a material of the protective layer is different from that of the sacrificial layer, and the protective layer is removed after all sacrificial layers are removed. ### Claim 10 (depends on 6) The method for forming a capacitor of claim 6, wherein the hard mask layer is patterned by a dry etching process, and the supporting layer is etched by the dry etching process to form the etching window exposing the sacrificial layer. ### Claim 11 (depends on 6) The method for forming a capacitor of claim 6, wherein the sacrificial layer is removed by a centrifugal wet cleaning process. ### Claim 12 (depends on 11) The method for forming a capacitor of claim 11, wherein a solution used in the wet cleaning process is an HF solution. ### Claim 13 (depends on 1) The method for forming a capacitor of claim 1, wherein two or more supporting layers are formed. ### Claim 14 (depends on 1) A capacitor, formed by the method of claim 1. ### Claim 15 (depends on 1) A method for forming a dynamic random-access memory (DRAM), comprising: forming a plurality of capacitors with the method of claim 1, distributed in an array. ### Claim 16 (depends on 15) A dynamic random-access memory (DRAM) formed with the method of claim 15, comprising the plurality of the capacitors distributed in the array.