# US 2021/0343701 A1 · Circuit that prevents device body diode conduction

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- Number: US 2021/0343701 A1
- Document ID: US20210343701A1
- Status: Published application
- Kind: A1
- Application number: 16/861,274
- Filed: 2020-04-29
- Published: 2021-11-04
- Earliest claimed: 2020-04-29
- Assignees: U.S. Army Combat Capabilities Development Command Army Research Laboratory
- Applicants: U.S Army Combat Capabilities Development Command, Army Research Laboratory
- Inventors: Damian P. Urciuoli
- Web page: https://patentgrep.com/patent/US20210343701A1

## CPC

- H03K 17/063: {in field-effect transistor switches}
- H10D 89/811: {using FETs as protective elements}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/8325: {Silicon carbide}
- H10D 89/611: {using diodes as protective elements}
- H10W 72/50: Bond wires
- H10W 90/00: Package configurations
- H03K 2017/066: {Maximizing the OFF-resistance instead of minimizing the ON-resistance}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/732: {between stacked chips}
- H10W 90/752: {between stacked chips}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A circuit comprising a first device (e.g., a high voltage MOSFET) coupled in series with a second device (e.g., a low voltage MOSFET or HEMT). The first device comprises a body diode. Additionally, the circuit comprises a diode coupled across the pair of devices. The diode is arranged antiparallel to the first device. In one exemplary embodiment, the first device is a SiC MOSFET and the second device is a Si MOSFET or GaN HEMT.

## Claims

### Claim 1

A circuit comprising:
a first device having a drain, source and gate with a body-diode coupled between the drain and the source;
a second device having a drain, source and gate;
a diode having a cathode and anode; and
where the source of the first device is connected to the source of the second device, and the cathode of the diode is connected to the drain of the first device and the anode of diode is connected to the drain of the second device, where the diode is antiparallel to the first device.

### Claim 2 (depends on 1)

The circuit of claim 1 wherein the first device is a MOSFET, high-voltage MOSFET, a SiC MOSFET or a MISFET.

### Claim 3 (depends on 1)

The circuit of claim 1 wherein the second device is a MOSFET, low-voltage MOSFET or a GaN HEMT.

### Claim 4 (depends on 1)

The circuit of claim 1 wherein the diode is a Junction Barrier Schottky (JBS) diode.

### Claim 5 (depends on 1)

The circuit of claim 1 wherein the first device is a high-voltage MOSFET, the second device is a low-voltage MOSFET, and the diode is a JBS diode.

### Claim 6 (depends on 5)

The circuit of claim 5 wherein the high voltage MOSFET is a SiC MOSFET and the low voltage MOSFET is a Si MOSFET.

### Claim 7

An integrated circuit structure comprising:
a first chip comprising a first device having a gate, source and drain with a body-diode coupled between the source and the drain, and a diode having a cathode and anode, where a first surface of the first chip comprises the drain of the first device and a cathode of the diode and a second surface of the first chip comprises the source of the first device, the gate of the first device, and an anode of the diode;
a second chip comprising a second device having a gate, drain and source, where a first surface of the second chip comprises the drain of the second device and the second surface comprises the source and gate of the second device;
wherein the second chip is arranged atop the first chip to position the source of the first device upon the source of the second device; and
wherein the drain of the second device is coupled to the anode of the diode.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7 wherein the first device is a MOSFET, high-voltage MOSFET, MISFET, or SiC MOSFET.

### Claim 9 (depends on 7)

The integrated circuit structure of claim 7 wherein the second device is a MOSFET, low-voltage MOSFET, Si MOSFET or GaN HEMT.

### Claim 10 (depends on 7)

The integrated circuit structure of claim 7 wherein the diode is a Junction Barrier Schottky (JBS) diode.

### Claim 11 (depends on 7)

The integrated circuit structure of claim 7 wherein the first MOSFET is a high-voltage MOSFET, the second MOSFET is a low-voltage MOSFET, and the diode is a JBS diode.

### Claim 12 (depends on 11)

The integrated circuit structure of claim 11 wherein the high voltage MOSFET is a SiC MOSFET and the low voltage MOSFET is a Si MOSFET.

### Claim 13

An integrated circuit structure comprising:
a first chip comprising a first device having a gate, source and drain with a body-diode coupled between the source and drain and a diode having a cathode and anode, where a first surface of the first chip comprises the drain of the first device and a cathode of the diode and a second surface of the first chip comprises the source of the first device and an anode of the diode;
a second chip comprising a second device having a gate, drain and source, where a first surface of the second chip comprises the drain of the second device and the second surface comprises the source and gate of the second device;
wherein the second chip is arranged atop the first chip to position the drain of the second device upon the anode of the diode; and
wherein the source of the second device is coupled to the source of the first device.

### Claim 14 (depends on 13)

The integrated circuit structure of claim 13 wherein the first device is a high-voltage MOSFET, MOSFET, MISFET or SiC MOSFET.

### Claim 15 (depends on 13)

The integrated circuit structure of claim 13 wherein the second device is a MOSFET, low-voltage MOSFET or GaN HEMT.

### Claim 16 (depends on 13)

The integrated circuit structure of claim 13 wherein the diode is a Junction Barrier Schottky (JBS) diode.

### Claim 17 (depends on 13)

The integrated circuit structure of claim 13 wherein the first device is a high-voltage MOSFET, the second device is a low-voltage MOSFET, and the diode is a JBS diode.

### Claim 18 (depends on 17)

The integrated circuit structure of claim 17 wherein the high voltage MOSFET is a SiC MOSFET and the low voltage MOSFET is a Si MOSFET.

### Claim 19 (depends on 1)

A method of operating a circuit of claim 1, comprising:
applying a signal to turn on the second device prior to applying a signal to turn on the first device.