# US 2021/0343684 A1 · Stacked decoupling capacitors with integration in a substrate

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- Number: US 2021/0343684 A1
- Document ID: US20210343684A1
- Status: Published application
- Kind: A1
- Application number: 16/864,363
- Filed: 2020-05-01
- Published: 2021-11-04
- Earliest claimed: 2020-05-01
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Jonghae KIM; Milind SHAH; Periannan CHIDAMBARAM
- Web page: https://patentgrep.com/patent/US20210343684A1

## CPC

- H10W 90/00: Package configurations
- H05K 1/186: {manufactured by mounting on or connecting to patterned circuits before or during embedding}
- H10D 1/692: {Electrodes}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/072: {of bump connectors}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H05K 1/0231: {Capacitors or dielectric substances}
- H05K 2201/10015: Non-printed capacitor
- H05K 2201/10159: Memory
- H05K 2201/10545: Related components mounted on both sides of the PCB
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/551: {Materials of bond wires}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.

## Claims

### Claim 1

An integrated circuit package, comprising:
a package substrate having a first capacitor embedded therein;
a semiconductor die disposed above the package substrate; and
a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.

### Claim 2 (depends on 1)

The integrated circuit package of claim 1, wherein the semiconductor die is coupled to the package substrate via a plurality of conductive pillars.

### Claim 3 (depends on 2)

The integrated circuit package of claim 2, wherein the conductive pillars comprise copper.

### Claim 4 (depends on 2)

The integrated circuit package of claim 2, wherein the first capacitor is electrically coupled to a portion of the conductive pillars.

### Claim 5 (depends on 1)

The integrated circuit package of claim 1, wherein the first capacitor includes an array of trench capacitors.

### Claim 6 (depends on 1)

The integrated circuit package of claim 1, wherein the first capacitor comprises a first set of terminals and a second set of terminals electrically coupled to the semiconductor die.

### Claim 7 (depends on 6)

The integrated circuit package of claim 6, wherein the first set of terminals is electrically coupled in parallel with each other, and wherein the second set of terminals is electrically coupled in parallel with each other.

### Claim 8 (depends on 6)

The integrated circuit package of claim 6, wherein the first capacitor comprises a third set of terminals and a fourth set of terminals electrically coupled to the second capacitor.

### Claim 9 (depends on 1)

The integrated circuit package of claim 1, wherein the first capacitor comprises:
a first plurality of terminals disposed on a first surface of the first capacitor and electrically coupled to the semiconductor die; and
a second plurality of terminals disposed on a second surface of the first capacitor and electrically coupled to a plurality of terminals of the second capacitor, the second surface being opposite from the first surface.

### Claim 10 (depends on 1)

The integrated circuit package of claim 1, wherein the package substrate includes a core substrate material.

### Claim 11 (depends on 10)

The integrated circuit package of claim 10, wherein the first capacitor intersects at least a portion of the core substrate material.

### Claim 12 (depends on 1)

The integrated circuit package of claim 1, wherein the package substrate is a coreless embedded trace substrate.

### Claim 13 (depends on 1)

The integrated circuit package of claim 1, wherein the first capacitor and the second capacitor are electrically coupled to one or more power rails of the semiconductor die.

### Claim 14 (depends on 1)

The integrated circuit package of claim 1, wherein the first capacitor and the second capacitor are electrically coupled to a reference potential node of the integrated circuit package.

### Claim 15 (depends on 1)

The integrated circuit package of claim 1, wherein the second capacitor is electrically coupled in parallel with the first capacitor.

### Claim 16 (depends on 1)

The integrated circuit package of claim 1, wherein the second capacitor is disposed directly under the first capacitor.

### Claim 17 (depends on 1)

An electronic device comprising the integrated circuit package of claim 1, wherein the first and second capacitors are electrically coupled to a power distribution network of the electronic device.

### Claim 18

A method of fabricating an integrated circuit package, comprising:
forming a package substrate having a first capacitor embedded therein;
disposing a semiconductor die above the package substrate; and
disposing a second capacitor below the package substrate such that the second capacitor is electrically coupled to the first capacitor.

### Claim 19 (depends on 18)

The method of claim 18, wherein disposing the semiconductor die above the package substrate comprises coupling the semiconductor die to the package substrate via a plurality of conductive pillars.

### Claim 20 (depends on 18)

The method of claim 18, wherein:
forming the package substrate comprises forming a first plurality of terminals on a first surface of the first capacitor and forming a second plurality of terminals on a second surface of the first capacitor, the second surface being opposite from the first surface;
disposing the semiconductor die above the package substrate comprises coupling the semiconductor die to the first plurality of terminals such that the first capacitor is electrically coupled to the semiconductor die through the first plurality of terminals; and
disposing the second capacitor below the package substrate comprises coupling the second capacitor to the second plurality of terminals such that the second capacitor is electrically coupled to the first capacitor through the second plurality of terminals.