# US 2021/0343607 A1 · Semiconductor structure

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- Number: US 2021/0343607 A1
- Document ID: US20210343607A1
- Status: Published application
- Kind: A1
- Application number: 17/373,948
- Filed: 2021-07-13
- Published: 2021-11-04
- Earliest claimed: 2020-04-03
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: ChihCheng LIU
- Web page: https://patentgrep.com/patent/US20210343607A1

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes: a substrate; an insulating region located in the substrate; a first conductor located above the insulating region and configured to collect charges; a second conductor at least partially located above the insulating region and configured to induce the charges of the first conductor; and a dielectric layer located between the first conductor and the second conductor to electrically insulate the first conductor from the second conductor.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
an insulating region, located in the substrate;
a first conductor, located above the insulating region and configured to collect charges;
a second conductor, at least partially located above the insulating region and configured to induce the charges of the first conductor; and
a dielectric layer, located between the first conductor and the second conductor and configured to electrically insulate the first conductor from the second conductor.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the insulating region comprises a shallow trench insulating structure.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the first conductor has a contact hole.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein a projection of the contact hole on the insulating region is U-shaped, V-shaped or C-shaped.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the second conductor is at least partially located in an opening of the contact hole.

### Claim 6 (depends on 3)

The semiconductor structure of claim 3, wherein the first conductor further comprises a metal layer, the metal layer being electrically connected with the contact hole.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the second conductor comprises polysilicon.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a first transistor and a second transistor, gate of each of the first transistor and the second transistor being electrically connected with the second conductor.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the first transistor is an N-Metal-Oxide-Semiconductor (NMOS) transistor, and the second transistor is a Positive Channel Metal Oxide Semiconductor (PMOS) transistor.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein a material of the dielectric layer is selected from at least one of silicon dioxide or silicon nitride.