# US 2021/0343597 A1 · Formation of hybrid isolation regions through recess and re-deposition

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- Number: US 2021/0343597 A1
- Document ID: US20210343597A1
- Status: Published application
- Kind: A1
- Application number: 16/933,648
- Filed: 2020-07-20
- Published: 2021-11-04
- Earliest claimed: 2020-04-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chung-Ting Ko; Chi On Chui
- Web page: https://patentgrep.com/patent/US20210343597A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6682: {the compound being a silane, e.g. disilane, methylsilane or chlorosilane}
- H10P 14/6689: {the compound being a silazane}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

## Claims

### Claim 1

A method comprising:
forming a semiconductor fin protruding higher than top surfaces of isolation regions, wherein the isolation regions extend into a semiconductor substrate;
etching a portion of the semiconductor fin to form a trench;
filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap;
performing a recessing process to recess the first dielectric material, wherein a recess is formed between opposing portions of the isolation regions; and
filling the recess with a second dielectric material, wherein the first dielectric material and the second dielectric material in combination form an additional isolation region, and wherein the second dielectric material has a second bandgap smaller than the first bandgap.

### Claim 2 (depends on 1)

The method of claim 1 further comprising, before the recessing, filling the trench with a third dielectric material, wherein in the recessing process, the third dielectric material is also recessed.

### Claim 3 (depends on 1)

The method of claim 1 further comprising performing a planarization process on the first dielectric material and the second dielectric material, wherein an exposed surface revealed by the planarization process includes a first surface of the first dielectric material, and a second surface of the second dielectric material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first surface forms a ring encircling the second surface.

### Claim 5 (depends on 1)

The method of claim 1 further comprising etching an additional dielectric material on a side of the additional isolation region, wherein in the etching the additional dielectric material, the second dielectric material has a lower etching rate than the first dielectric material.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first dielectric material is a homogenous material, and the first dielectric material fills an entirety of the trench before the recessing process is performed.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first dielectric material comprises a first seam, and the second dielectric material comprises a second seam over the first seam.

### Claim 8 (depends on 1)

The method of claim 1, wherein the trench comprises a portion lower than the isolation regions.

### Claim at position 9

9-20. (canceled)

### Claim 21

A method comprising:
a semiconductor substrate;
forming a first source/drain region and a second source/drain region;
forming a dielectric region separating the first source/drain region and the second source/drain region, wherein the forming the dielectric region comprises:
forming a first layer having a first bandgap, the first layer comprising:
a lower portion with a bottom contacting the semiconductor substrate; and
an upper portion higher than the lower portion, wherein the upper portion is thinner than the lower portion; and
forming a second layer encircled by the upper portion of the first layer, wherein the second layer has a second bandgap lower than the first bandgap.

### Claim 22 (depends on 21)

The method of claim 21, wherein the forming the first layer comprises:
etching the semiconductor substrate to form a trench;
filling the trench with the first layer; and
etching the first layer.

### Claim 23 (depends on 22)

The method of claim 22 further comprising, after the filling the trench with the first layer and before the etching the first layer, depositing a third layer in the trench and over the first layer.

### Claim 24 (depends on 23)

The method of claim 23, wherein when the first layer is etched, the third layer is also etched.

### Claim 25 (depends on 24)

The method of claim 24, wherein when the first layer and the third layer are etched, the third layer has a greater etching rate than the first layer.

### Claim 26 (depends on 21)

The method of claim 21, wherein the lower portion has a first thickness, and the upper portion has a second thickness smaller than the first thickness.

### Claim 27 (depends on 21)

The method of claim 21 further comprising:
forming a gate stack, wherein the lower portion is joined to the upper portion at a level lower than a top surface of the gate stack.

### Claim 28 (depends on 21)

The method of claim 21, wherein the lower portion of the first layer is joined to the upper portion at the level lower than a top surface of a semiconductor fin over the semiconductor substrate.

### Claim 29 (depends on 21)

The method of claim 21, wherein the first layer comprises a first seam therein, and the second layer comprises a second seam therein, and the first layer and the second layer are separated from each other by a bottom portion of the second layer.

### Claim 30

A method comprising:
removing a dummy gate stack to form a trench between a first gate spacer and a second gate spacer;
extending the trench down into a semiconductor fin;
forming an isolation region filling the trench, the forming the isolation region comprising:
filling a first dielectric material into the trench, the first dielectric material comprising a first portion higher than the semiconductor fin and a second portion lower than the semiconductor fin, wherein the first portion is narrower than the second portion; and
filling a second dielectric material into the trench, the second dielectric material being encircled by the first portion of the first dielectric material, wherein the second dielectric material comprises a third portion higher than the semiconductor fin and a fourth portion lower than the semiconductor fin, and wherein the fourth portion is narrower than the third portion.

### Claim 31 (depends on 30)

The method of claim 30, wherein the first dielectric material has a first bandgap greater than a second bandgap of the second dielectric material.

### Claim 32 (depends on 30)

The method of claim 30, wherein the third portion and the fourth portion comprise a first seam and a second seam, respectively, and the first seam is separated from the second seam by a portion of the second dielectric material.