# US 2021/0343584 A1 · Semiconductor device manufacturing method and semiconductor device

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- Number: US 2021/0343584 A1
- Document ID: US20210343584A1
- Status: Published application
- Kind: A1
- Application number: 17/375,500
- Filed: 2021-07-14
- Published: 2021-11-04
- Earliest claimed: 2019-03-18
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Mie Matsuo
- Web page: https://patentgrep.com/patent/US20210343584A1

## CPC

- H10P 90/1916: {with separation or delamination along an ion implanted layer, e.g. Smart-cut}
- H10P 10/12: {Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 90/1914: {using bonding}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 72/7416: {used during dicing or grinding}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; for a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.

## Claims

### Claim 1

A semiconductor device comprising:
a first substrate, the first substrate being a whole wafer;
a first layer arranged in a region of the first substrate excluding an outer peripheral portion thereof; and
a first film including a first semiconductor circuit arranged above the first layer,

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the first layer is any of:
a layer that an elemental ion is injected to a predetermined depth of the first substrate or a layer arranged on the first substrate,
a layer that the predetermined depth of the first substrate or the layer arranged on the first substrate is irradiated with a laser, and
a layer that a region of the first substrate inside the outer peripheral portion thereof is anodically oxidized.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second substrate, the second substrate being a whole wafer;
a second film including a second semiconductor circuit arranged on the second substrate; and
a second layer arranged with a predetermined width on the second film at an outer peripheral portion of the second substrate.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein
the second layer is any of:
a layer with an increased surface roughness of the second film at the outer peripheral portion of the second substrate,
a layer with a groove formed to the second film at the outer peripheral portion of the second substrate, and
a step formed to the second film at the outer peripheral portion of the second substrate such that the outer peripheral portion is provided lower than a bonded surface between the first substrate and the second substrate.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
a third layer not connected to the first layer is provided above the first film at the outer peripheral portion of the first substrate.