# US 2021/0343344 A1 · Memory Device and Programming Method Thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0343344 A1 - Document ID: US20210343344A1 - Status: Published application - Kind: A1 - Application number: 16/889,746 - Filed: 2020-06-01 - Published: 2021-11-04 - Earliest claimed: 2020-04-29 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Hongtao Liu; Ying Huang; Wenzhe Wei; Song Min Jiang; Dejia Huang; Wen Qiang Chen - Web page: https://patentgrep.com/patent/US20210343344A1 ## CPC - G11C 16/10: Programming or data input circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/24: Bit-line control circuits - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G11C 16/30: Power supply circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed. ## Claims ### Claim 1 A programming method for a memory device, the programming method comprising: moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed. ### Claim 2 (depends on 1) The programming method of claim 1, wherein: the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer immediately after a coarse programming operation for the first word line; or the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer immediately after a coarse programming operation for a second word line next to the first word line. ### Claim 3 (depends on 1) The programming method of claim 1, wherein the plurality of first charge carriers at the shallow energy level are moved from a tunneling layer to the channel in the substrate layer. ### Claim 4 (depends on 1) The programming method of claim 1, wherein the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer as a result of an electric field applied to the memory cell. ### Claim 5 (depends on 4) The programming method of claim 4, wherein a plurality of second charge carriers at a deep energy level are prohibited from migrating to the channel in the substrate layer when the electric field is appropriately controlled, and the plurality of second charge carriers are trapped in a storage layer. ### Claim 6 (depends on 1) The programming method of claim 1, wherein: at least one selected word line is grounded, a plurality of bit lines are grounded, a common source line is grounded, a well of the substrate layer is grounded, a plurality of select cells are turned off, a first nonzero voltage is applied to at least one unselected word line, and a second nonzero voltage is applied to a plurality of dummy lines, so as to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer. ### Claim 7 (depends on 6) The programming method of claim 6, wherein the first nonzero voltage is larger than 0 volts but lower than a voltage of a programming pulse, and the second nonzero voltage is larger than 0 volts but lower than the first nonzero voltage. ### Claim 8 (depends on 1) The programming method of claim 1, wherein: a plurality of bit lines are floating, a common source line is floating, a plurality of ground selection lines are floating, a plurality of string select lines are floating, at least one unselected word line is floating, a plurality of dummy lines are floating, at least one selected word line is grounded, and a third nonzero voltage is applied to a well of the substrate layer, so as to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer. ### Claim 9 (depends on 8) The programming method of claim 8, wherein the third nonzero voltage is larger than 0 volts but lower than a voltage of a programming pulse. ### Claim 10 (depends on 1) The programming method of claim 1, wherein at least one selected word line is grounded, and channel potential of the memory cell to be programmed is higher than 0 volts, so as to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer. ### Claim 11 A memory device, comprising: a plurality of memory cells; a voltage generation circuit, configured to generate a plurality of voltages applied to at least the plurality of memory cells according to a plurality of control signals; and a control circuit, configured to generate the plurality of control signals to the voltage generation circuit according to a programming method, wherein the programming method comprises: moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed. ### Claim 12 (depends on 11) The memory device of claim 11, wherein: the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer immediately after a coarse programming operation for the first word line; or the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer immediately after a coarse programming operation for a second word line next to the first word line. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the plurality of first charge carriers at the shallow energy level are moved from a tunneling layer to the channel in the substrate layer. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the plurality of first charge carriers at the shallow energy level are moved to the channel in the substrate layer as a result of an electric field applied to the memory cell. ### Claim 15 (depends on 14) The memory device of claim 14, wherein a plurality of second charge carriers at a deep energy level are prohibited from migrating to the channel in the substrate layer when the electric field is appropriately controlled, and the plurality of second charge carriers are trapped in a storage layer. ### Claim 16 (depends on 11) The memory device of claim 11, wherein: at least one selected word line is grounded, a plurality of bit lines are grounded, a common source line is grounded, a well of the substrate layer is grounded, a plurality of select cells are turned off, a first nonzero voltage is applied to at least one unselected word line, and a second nonzero voltage is applied to a plurality of dummy lines, so as to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer. ### Claim 17 (depends on 16) The memory device of claim 16, wherein the first nonzero voltage is larger than 0 volts but lower than a voltage of a programming pulse, and the second nonzero voltage is larger than 0 volts but lower than the first nonzero voltage. ### Claim 18 (depends on 11) The memory device of claim 11, wherein: a plurality of bit lines are floating, a common source line is floating, a plurality of ground selection lines are floating, a plurality of string select lines are floating, at least one unselected word line is floating, a plurality of dummy lines are floating, at least one selected word line is grounded, and a third nonzero voltage is applied to a well of the substrate layer, so as to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer. ### Claim 19 (depends on 18) The memory device of claim 18, wherein the third nonzero voltage is larger than 0 volts but lower than a voltage of a programming pulse. ### Claim 20 (depends on 11) The memory device of claim 11, wherein at least one selected word line is grounded, and channel potential of the memory cell to be programmed is higher than 0 volts, so as to move the plurality of first charge carriers at the shallow energy level to the channel in the substrate layer.