# US 2021/0343331 A1 · Partial refresh technique to save memory refresh power > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0343331 A1 - Document ID: US20210343331A1 - Status: Published application - Kind: A1 - Application number: 17/377,799 - Filed: 2021-07-16 - Published: 2021-11-04 - Earliest claimed: 2017-08-02 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Jungwon SUH; Yanru LI; Michael Hawjing LO; Dexter Tamio CHUN - Web page: https://patentgrep.com/patent/US20210343331A1 ## CPC - G11C 11/40622: {Partial refresh of memory arrays} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1045: {Read-write mode select circuits} - G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh} - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 2211/406: Refreshing of dynamic cells - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped. ## Claims ### Claim 1 An apparatus, comprising: a memory device, comprising: a plurality of DRAM memory cells; and a partial array refresh (PAR) enable register which comprises a partial array auto-refresh (PAAR) enable bit, wherein the PAAR enable bit indicates whether or not a PAAR is enabled, and a partial array refresh (PAR) mask register, wherein when the memory device is in an auto-refresh mode and when the PAAR is enabled, the memory device is configured to mask a portion of the plurality of DRAM memory cells from being refreshed based on the PAR mask register upon the memory device receiving a refresh (REF) command. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the PAR enable register is implemented using one or more mode registers and the PAAR enable bit is set or unset upon the memory device receiving a mode register write command along with a corresponding mode value. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the PAR enable register further comprises a partial array self-refresh (PASR) enable bit, wherein the PASR enable bit indicates whether or not a PASR is enabled. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the PASR enable bit and the PAAR enable bit of the PAR enable register indicate whether one, both, or none of the partial array auto-refresh (PAAR) and the partial array self-refresh (PASR) are enabled. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising a system-on-chip (SOC) configured to provide commands to the memory device over a link. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the REF command comprises a refresh-per-bank command or a refresh-all-banks command. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the memory device further comprises an input/output I/O circuit configured to interface with the SOC over the link and write data to and read data from the plurality of DRAM memory cells; and wherein the memory device is configured to refresh a subset of the plurality of DRAM memory cells selected in accordance with the PAR mask register without the I/O circuit receiving the REF commands from the SOC when the memory device is in a self-refresh mode and a partial array self-refresh PASR and the PAAR are enabled and wherein the memory device is further configured to refresh the subset of the plurality of DRAM memory cells selected in accordance with the PAR mask register upon the I/O circuit receiving the REF command from the SOC when the PAAR is enabled. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the SOC is configured to adjust an interval in between issuing the REF commands to the memory device based on the refreshing subset. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the plurality of DRAM memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of segment mask bits, each segment mask bit corresponding to a segment of a bank and indicating whether a refresh is enabled or disabled for the corresponding segment, and wherein the memory device is configured to skip refreshing of each segment of a current bank whose corresponding segment mask bit indicates that the refresh is disabled when the REF command is a refresh-per-bank command and the PAAR enable bit is set. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the plurality of DRAM memory cells is partitioned into a plurality of banks, wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and wherein the memory device is configured to skip the refreshing of a current bank when the corresponding bank mask bit indicates that the refresh is disabled when the PAAR is enabled, and the REF command is a refresh-per-bank command. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the plurality of DRAM memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of segment mask bits, each segment mask bit corresponding to a segment of a bank and indicating whether a refresh is enabled or disabled for the corresponding segment, and wherein the memory device is configured to, for each bank, skip refreshing of each segment of that bank whose corresponding segment mask bit indicates that the refresh is disabled when the PAAR is enabled, and the REF command is a refresh-all-banks command. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the plurality of DRAM memory cells is partitioned into a plurality of banks, wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and wherein the memory device is configured to skip the refreshing of each bank whose corresponding bank mask bit indicates that the refresh is disabled the PAAR is enabled, and the REF command is a refresh-all-banks command. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the plurality of DRAM memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and wherein the memory device is configured to skip refreshing of each bank whose corresponding bank mask bit indicates that the refresh is disabled for that bank, and for each bank whose corresponding bank mask bit indicates that the refresh is enabled for that bank, skip refreshing each segment of that bank whose corresponding segment mask bit indicates that the refresh is disabled when the PAAR is enabled. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the apparatus is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smart phone a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle. ### Claim 15 An apparatus, comprising: a system-on-chip (SOC) configured to communicate with a memory device over a link, wherein the memory device comprises: a plurality of DRAM memory cells; a partial array refresh PAR enable register which comprises a partial array auto-refresh (PAAR) enable bit, wherein the PAAR enable bit indicates whether or not a PAAR is enabled; and a PAR mask register, wherein the SOC is configured to instruct the memory device to enter into a self-refresh mode to cause the memory device to refresh a subset of the memory cells selected in accordance with the PAR mask register without receiving refresh REF commands from the SOC when a partial array self-refresh (PASR) is enabled by a PASR enable bit set by the PAR enable register, and wherein the SOC is configured to issue the REF command to the memory device to cause the memory device to refresh the subset of the memory cells selected in accordance with the PAR mask register when the memory device is in an auto-refresh mode and the PAAR is enabled. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the memory device comprises a plurality of mode registers MR, the MR comprising the PAR mask register and the PAR enable register including a plurality of enable bits including a PASR enable bit and the PAAR enable bit, the PASR enable bit indicating whether the PASR is enabled or disabled, and the PAAR enable bit indicating whether the PAAR is enabled or disabled. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the SOC is configured to issue a mode register write MRW command with a corresponding mode value of the PAAR enable bit to the memory device, and for each mode register used to implement the PAR mask register, issue the MRW command with the corresponding mode value to the memory device so as to cause a mask value to be written to the PAR mask register, the mask value indicating a refresh skip region comprising one or more portions of the plurality of memory cells that do not require refreshing. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the SOC is configured to adjust an interval in between issuing successive REF commands to the memory device based on the refresh skip region. ### Claim 19 A method for reducing memory power consumption in an apparatus of a computing system, wherein the apparatus comprises a system-on-chip (SOC) and a memory device configured to communicate with each other over a link, wherein the memory device comprises: a plurality of memory cells; and a plurality of mode registers MR comprising a partial array refresh PAR enable register and a PAR mask register, the PAR enable register including a partial array self-refresh PASR enable bit and a partial array auto-refresh PAAR enable bit, the PASR enable bit indicating whether PASR is enabled or disabled, and the PAAR enable bit indicating whether PAAR is enabled or disabled, and wherein the method comprises: issuing, by the SOC, a mode register write MRW command with a corresponding mode value of the PAAR enable bit to the memory device; issuing, by the SOC, for each mode register used to implement the PAR mask register, a MRW command with a corresponding mode value to the memory device so as to cause a mask value to be written to the PAR mask register, the mask value corresponding to a refresh skip region; issuing, by the SOC, a REF command to the memory device; and skipping, by the memory device, refreshing of the refresh skip region based on the PAR mask register when the REF command is issued by the SOC and the PAAR enable bit is set. ### Claim 20 An apparatus, comprising: a system-on-chip SOC configured to communicate with a memory device over a link, wherein the memory device comprises: a plurality of memory cells; a partial array refresh PAR enable register which comprises a partial array auto-refresh PAAR enable bit, wherein the PAAR enable bit indicates whether or not a PAAR is enabled; and a PAR mask register, wherein the SOC is configured to issue a refresh REF command to the memory device over the link to cause the memory device to refresh a subset of the memory cells selected in accordance with the PAR mask register when the memory device is in an auto-refresh mode and the PAAR is enabled on the memory device.