# US 2021/0343322 A1 · Ferroelectric memory cell access

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- Number: US 2021/0343322 A1
- Document ID: US20210343322A1
- Status: Published application
- Kind: A1
- Application number: 17/323,968
- Filed: 2021-05-18
- Published: 2021-11-04
- Earliest claimed: 2019-07-15
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Umberto Di Vincenzo
- Web page: https://patentgrep.com/patent/US20210343322A1

## CPC

- G11C 11/2259: {Cell access}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2257: {Word-line or row circuits}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/2293: {Timing circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

## Claims

### Claim 1

(canceled)

### Claim 2

A method, comprising:
selecting, as part of an access operation for a memory cell, a digit line from a set of digit lines;
coupling the selected digit line with a capacitor of the memory cell;
coupling a subset of the set of digit lines with a plate, the plate coupled with the memory cell; and
increasing, after coupling the subset of the set of digit lines with the plate, a voltage of the plate from a first voltage to a second voltage while the selected digit line is coupled with the capacitor.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
increasing, before coupling the selected digit line with the capacitor, a voltage of the selected digit line from the first voltage to the second voltage.

### Claim 4 (depends on 3)

The method of claim 3, wherein coupling the selected digit line with the capacitor comprises:
activating, based at least in part on increasing the voltage of the selected digit line, a word line coupled with the memory cell.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
deactivating the word line, after increasing the voltage of the plate, to decouple the capacitor from the selected digit line; and
decreasing the voltage of the plate and the voltage of the selected digit line to the first voltage after deactivating the word line.

### Claim 6 (depends on 2)

The method of claim 2, further comprising:
coupling the selected digit line with the plate during the access operation.

### Claim 7 (depends on 6)

The method of claim 6, wherein coupling the selected digit line with the plate occurs after the voltage of the plate reaches the second voltage.

### Claim 8 (depends on 2)

The method of claim 2, further comprising:
coupling the selected digit line to a voltage source after the plate reaches the second voltage, the voltage source biased at the second voltage.

### Claim 9 (depends on 2)

The method of claim 2, further comprising:
activating, before increasing the voltage of the plate from the first voltage to the second voltage, a latch operable to sense a logic state stored by the memory cell.

### Claim 10 (depends on 9)

The method of claim 9, wherein the memory cell is operable to store one of a first logic state or a second logic state, and wherein the memory cell is at least partially written to the first logic state before the latch is activated.

### Claim 11 (depends on 2)

The method of claim 2, wherein the subset of the set of digit lines comprises unselected digit lines.

### Claim 12

An apparatus, comprising:
a set of memory cells;
a set of digit lines couplable with the set of memory cells;
a plate coupled with the set of memory cells; and
a controller coupled with the set of digit lines and the plate, wherein the controller is operable to cause the apparatus to:
select, as part of an access operation for a memory cell of the set of memory cells, a digit line from the set of digit lines;
couple the selected digit line with a capacitor of the memory cell;
couple a subset of the set of digit lines with the plate; and
increase, after coupling the subset of the set of digit lines with the plate, a voltage of the plate from a first voltage to a second voltage while the selected digit line is coupled with the capacitor.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the controller is further operable to cause the apparatus to:
increase, before coupling the selected digit line with the capacitor, a voltage of the selected digit line from the first voltage to the second voltage.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein, to couple the selected digit line with the capacitor, the controller is further operable to cause the apparatus to:
activate, based at least in part on increasing the voltage of the selected digit line, a word line coupled with the memory cell.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the controller is further operable to cause the apparatus to:
deactivate the word line, after increasing the voltage of the plate, to decouple the capacitor from the selected digit line; and
decrease the voltage of the plate and the voltage of the selected digit line to the first voltage after deactivating the word line.

### Claim 16 (depends on 12)

The apparatus of claim 12, wherein the controller is further operable to cause the apparatus to:
couple the selected digit line with the plate after the plate reaches the second voltage.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein coupling the selected digit line with the plate occurs after the voltage of the plate reaches the second voltage.

### Claim 18 (depends on 12)

The apparatus of claim 12, wherein the controller is further operable to cause the apparatus to:
couple the selected digit line to a voltage source after the plate reaches the second voltage, the voltage source biased at the second voltage.

### Claim 19 (depends on 12)

The apparatus of claim 12, wherein the controller is further operable to cause the apparatus to:
activate, before increasing the voltage of the plate from the first voltage to the second voltage, a latch operable to sense a logic state stored by the memory cell.

### Claim 20 (depends on 12)

The apparatus of claim 12, wherein the subset of the set of digit lines comprises unselected digit lines.

### Claim 21

An apparatus, comprising:
a memory cell;
a plate line coupled with the memory cell; and
a set of digit lines, the set of digit lines comprising:
a digit line operable to be selected and coupled with a capacitor of the memory cell as part of an access operation for the memory cell; and
a subset of digit lines operable to be coupled with the plate during the access operation, wherein the plate is configured to have a voltage increased from a first voltage to a second voltage while the selected digit line is coupled with the capacitor.