# US 2021/0342284 A1 · Networked Computer With Multiple Embedded Rings > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342284 A1 - Document ID: US20210342284A1 - Status: Published application - Kind: A1 - Application number: 17/305,680 - Filed: 2021-07-13 - Published: 2021-11-04 - Earliest claimed: 2019-03-27 - Assignees: Graphcore Limited - Applicants: Graphcore Limited - Inventors: Simon KNOWLES; Hachem YASSINE - Web page: https://patentgrep.com/patent/US20210342284A1 ## CPC - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 15/17318: {Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all} - G06F 13/4013: {with data re-ordering, e.g. Endian conversion} - G06F 13/4063: {Device-to-bus coupling} - G06F 15/173: using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake - G06F 15/17381: {Two dimensional, e.g. mesh, torus} - G06F 15/17387: {Three dimensional, e.g. hypercubes} - H04L 45/16: Multipoint routing - H04L 49/109: Integrated on microchip, e.g. switch-on-chip - G06F 2213/0038: System on Chip - H04L 49/25: Routing or path finding in a switch fabric - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A network comprising interconnected first and second processors, each processor comprising one or more of: multiple processing units arranged on a chip configured to execute program code; an on-chip interconnect comprising groups of exchange paths connected to receive data from corresponding groups of the processing units; external interfaces configured to communicate data off-chip as packets, each having a destination address, external interfaces of the first and second processors being connected by an external link; multiple exchange blocks, each connected to groups of the exchange paths; a routing bus configured to route packets between the exchange blocks and the external interfaces. Processing units of the first processor generate off-chip packets such that the group of processing units serviced by the first exchange block on the first processor address off-chip packets to the group of processing units on the second processor serviced by the corresponding first exchange block of the second processor. ## Claims ### Claim 1 A network comprising a first processor interconnected with a second processor, each processor comprising one or more of: a plurality of processing units arranged on a chip, each processing unit being configured to execute program code; an on-chip interconnect arranged to enable the program code to run on the processing units to exchange data between the processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group connected to receive data from a corresponding group of the processing units; a plurality of external interfaces configured to communicate data off chip as packets, each packet having a destination address identifying a destination of the packet, a first external interface of the first processor being connected by an external link to a corresponding first external interface of the second processor; a plurality of exchange blocks connected to the groups of exchange paths; and a routing bus configured to route packets between the exchange blocks and the external interfaces; wherein processing units of the first processor are configured to generate off chip packets addressed to processing units of the second processor such that a group of processing units serviced by a first exchange block on the first processor are configured to address off chip packets to a group of processing units on the second processor serviced by a corresponding first exchange block of the second processor. ### Claim 2 (depends on 1) The network of claim 1, wherein each processor comprises a plurality of exchange blocks in a first portion of the chip and a plurality of exchange blocks in a second portion of the chip, wherein the on-chip interconnect extends between exchange blocks in the first portion and exchange blocks in the second portion. ### Claim 3 (depends on 2) The network of claim 2, wherein each processor comprises eight exchange blocks in the first portion of the chip and eight exchange blocks in the second portion of the chip. ### Claim 4 (depends on 2) The network of claim 2, wherein the processing units of the first processor are configured to generate packets addressed to processing units of the second processor such that processing units serviced by each exchange block of the first processor transmit off-chip packets addressed only to processing units serviced by corresponding exchange blocks of the second processor. ### Claim 5 (depends on 1) The network of claim 1, wherein the routing bus is configured to route packets from certain exchange blocks only to certain external interfaces and wherein the routing bus is configured to trap as an error packets which are incorrectly addressed by comparing an address of a packet with routing requirements in a routing register. ### Claim 6 (depends on 1) The network of claim 1, wherein the routing bus has multiple lanes, each lane being unidirectional. ### Claim 7 (depends on 1) The network of claim 1, wherein the routing bus has ingress and egress ports at at least one exchange block for incoming and outgoing packets. ### Claim 8 (depends on 1) The network of claim 1, wherein the routing bus has ingress and egress ports at at least one external interface. ### Claim 9 (depends on 1) The network of claim 1, wherein the first processor has additional external interfaces connected to corresponding additional processors. ### Claim 10 (depends on 1) The network of claim 1, wherein the first processor has a second interface for connecting to a third processor, and wherein the first and second interfaces lie in the second portion of the chip. ### Claim 11 (depends on 10) The network of claim 10, wherein the chip lies in an orientation relative to other chips such that the second interface is connected to a third processor in a southern orientation relative to the first processor. ### Claim 12 (depends on 10) The network of claim 10, wherein the first processor has a third external interface which is connected to a fourth processor in a southern orientation with respect to the first processor. ### Claim 13 (depends on 12) The network of claim 12, wherein logical identifiers are allocated to each of the second, third and fourth processors which are connected to the first processor, and wherein the first processor is configured to only address packets to these logical identifiers. ### Claim 14 (depends on 1) The network of claim 1, wherein the first processor has additional external interfaces connected to corresponding additional processors, and wherein each processor has three processors connected directly to it and is configured to operate a routing domain having respective first to fourth logical identifiers to identify itself and each of those three connected processors. ### Claim 15 (depends on 14) The network of claim 14, wherein each logical identifier is mapped to a physical identifier of a corresponding one of the processors. ### Claim 16 (depends on 1) The network of claim 1, wherein the routing bus has multiple lanes, each lane being unidirectional, and wherein each chip has four portions corresponding to respective edges of the chip, and wherein a first set of the lanes are southgoing between a top edge and a bottom edge, and a second set of the lanes are northgoing between the bottom edge and the top edge. ### Claim 17 (depends on 16) The network of claim 16, wherein the packets sourced by exchange blocks in a top portion of a chip are only addressed to processors connected to the right or bottom of that chip and packets sourced by exchange blocks on a bottom portion of the chip are only addressed to processors connected to the right or top of that chip. ### Claim 18 (depends on 16) The network of claim 16, wherein the first and second processors are carried on a card, and wherein: the first chip is oriented in a first orientation in which top and bottom portions of the chip have respective interfaces on a left portion for connection externally of the card and respective interfaces on a right portion for connections internally of the card; and the second chip is oriented in a reverse orientation such that its top portion aligns with the bottom portion of the first processor and its bottom portion aligns with the top portion of the first processor. ### Claim 19 (depends on 18) The network of claim 18, wherein the interfaces on the left portion of each of the first and second processors are reserved for connections externally of the card. ### Claim 20 (depends on 19) The network of claim 19, wherein at least one of the interfaces on each left portion is available for connection to a host. ### Claim 21 (depends on 18) The network of claim 18, wherein the chips of the card are configured identically in relation to their internal routing protocols and arrangements of routing bus and exchange blocks. ### Claim 22 (depends on 18) The network of claim 18, wherein processors oriented in the first orientation are assigned even numbers as physical identifiers and processors oriented in the reverse orientation are assigned odd numbers as physical identifiers. ### Claim 23 (depends on 18) The network of claim 18, comprising multiple cards connected using external interfaces of the processors on the respective left edges. ### Claim 24 A processor comprising: an on-chip interconnect configured to exchange data among a plurality of processing units, wherein the on-chip interconnect comprises multiple groups of exchange paths, each group of exchange paths connected to receive data from a corresponding group of the processing units; a plurality of external interfaces configured to communicate data off chip as off chip packets having destination addresses, wherein the processor is interconnected with an additional processor, and wherein a first external interface of the first processor is connected by an external link to a corresponding first external interface of the additional processor; a plurality of exchange blocks connected to the groups of exchange paths; and a routing bus configured to route packets between the exchange blocks and the external interfaces; wherein the plurality of processing units of the processor are configured to generate the off chip packets addressed to another plurality of processing units of the additional processor such that a group of processing units serviced by a first exchange block on the processor are configured to address the off chip packets to a group of processing units on the additional processor serviced by a corresponding first exchange block of the additional processor.