# US 2021/0342279 A1 · Non-interrupting portable page request interface

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- Number: US 2021/0342279 A1
- Document ID: US20210342279A1
- Status: Published application
- Kind: A1
- Application number: 16/862,858
- Filed: 2020-04-30
- Published: 2021-11-04
- Earliest claimed: 2020-04-30
- Assignees: Red Hat, Inc.
- Applicants: Red Hat, Inc.
- Inventors: Michael Tsirkin; David Gilbert
- Web page: https://patentgrep.com/patent/US20210342279A1

## CPC

- G06F 13/1673: {using buffers}
- G06F 9/30029: {Logical and Boolean instructions, e.g. XOR, NOT}
- G06F 9/45545: {Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 12/0882: Page mode
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 2009/45579: {I/O management, e.g. providing access to device drivers or storage}
- G06F 2009/45583: {Memory management, e.g. access or allocation}
- G06F 2212/1024: Latency reduction
- G06F 2212/151: Emulated environment, e.g. virtual machine
- G06F 2212/651: Multi-level translation tables
- G06F 2213/0024: Peripheral component interconnect [PCI]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for memory management for virtual machines. An example method may include generating, by a Peripheral Component Interconnect (PCI) device comprising an input/output memory management unit (IOMMU), a first bit sequence and generating a second sequence by applying a predetermined transformation to the first bit sequence. The method may then write the second bit sequence to a memory buffer, read a first value from the memory buffer, write the first bit sequence to the memory buffer, and read a second value from the memory buffer. Responsive to determining that the second value does not match the first value, the method may associate a writable attribute with an IOMMU page table entry associated with the memory buffer.

## Claims

### Claim 1

A method comprising:
generating, by a processing device in communication with an input/output memory management unit (IOMMU), a first bit sequence;
generating a second sequence by applying a predetermined transformation to the first bit sequence;
writing the second bit sequence to a memory buffer;
reading a first value from the memory buffer;
writing the first bit sequence to the memory buffer;
reading a second value from the memory buffer; and
responsive to determining that the second value does not match the first value, associating a writable attribute with an IOMMU page table entry associated with the memory buffer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the transformation includes at least one of inverting one or more bits in each byte of the bit sequence, incrementing each byte of the bit sequence by one, or applying a bitwise XOR to each byte of the bit sequence.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
responsive to determining that the second value matches the first value, requesting the IOMMU page table entry be write enabled.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
responsive to determining that the second value matches the first value, selecting a new memory page to write the first bit sequence to.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
appending, to a page table of the IOMMU, a plurality of records referencing present memory pages associated with a task running on the virtual machine; and
appending, to the page table of the IOMMU, a plurality of records referencing read-only memory pages associated with the task, wherein the read-only memory pages are indicated as read-only in the page table.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
responsive to determining that the page table of the IOMMU and a page table of the hypervisor use the same page table format, pointing the IOMMU to the page table of the hypervisor.

### Claim 7 (depends on 1)

The method of claim 1, wherein the processing device is comprised by a Peripheral Component Interconnect (PCI) device.

### Claim 8

A system, comprising:
a memory;
input/output memory management unit (IOMMU) coupled to the memory; and
a processing device operatively coupled to the IOMMU, the processing device configured to:
generate a first bit sequence;
generate a second sequence by applying a predetermined transformation to the first bit sequence;
write the second bit sequence to a memory buffer;
read a first value from the memory buffer;
write the first bit sequence to the memory buffer;
read a second value from the memory buffer; and
responsive to determining that the second value does not match the first value, associate a writable attribute with an IOMMU page table entry associated with the memory buffer.

### Claim 9 (depends on 8)

The system of claim 8, wherein the transformation includes at least one of inverting one or more bits in each byte of the bit sequence, incrementing each byte of the bit sequence by one, or applying a bitwise XOR to each byte of the bit sequence.

### Claim 10 (depends on 8)

The system of claim 8, wherein the processing device is further to: responsive to determining that the second value matches the first value, request the IOMMU page table entry be write enabled.

### Claim 11 (depends on 8)

The system of claim 8, wherein the processing device is further to: responsive to determining that the second value matches the first value, select a new memory page to write the first bit sequence to.

### Claim 12 (depends on 11)

The system of claim 11, wherein the processing device is further to:
append, to a page table of the IOMMU, a plurality of records referencing present memory pages associated with a task running on the virtual machine; and
append, to the page table of the IOMMU, a plurality of records referencing read-only memory pages associated with the task, wherein the read-only memory pages are indicated as read-only in the page table.

### Claim 13 (depends on 18)

The system of claim 18, wherein the processing device is comprised by a Peripheral Component Interconnect (PCI) device.

### Claim 14

A method comprising:
running, by a host computer system, a hypervisor managing a virtual machine in communication with a peripheral device, wherein the peripheral device comprises an input/output memory management unit (IOMMU);
appending, to a page table of the IOMMU, a plurality of records referencing present memory pages associated with a task running on the virtual machine; and
appending, to the page table of the IOMMU, a plurality of records referencing read-only memory pages associated with the task, wherein the read-only memory pages are indicated as read-only in the page table.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
accessing, from the hypervisor, a memory page associated with the task.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
responsive to determining that a record referencing a memory page is not present in the page table of the IOMMU, requesting the memory page from a device driver of the virtual machine; and
accessing the memory page.

### Claim 17 (depends on 14)

The method of claim 14, further comprising:
responsive to determining that the page table of the IOMMU and a page table of the hypervisor use the same page table format, pointing the IOMMU to the page table of the hypervisor.

### Claim 18 (depends on 14)

The method of claim 14, further comprising:
generating a first bit sequence;
generating a second bit sequence by applying a predetermined transformation to the first bit sequence;
writing the second bit sequence to a memory buffer, wherein the memory buffer comprises a memory page referenced by the page table of the IOMMU;
reading a first value from the memory buffer;
writing the first bit sequence to the memory buffer;
reading a second value from the memory buffer; and
responsive to determining that the second value does not match the first value, associating a writable attribute with an IOMMU page table entry associated with the memory buffer.

### Claim 19 (depends on 18)

The method of claim 18, wherein the transformation includes at least one of inverting one or more bits in each byte of the bit sequence, incrementing each byte of the bit sequence by one, or applying a bitwise XOR to each byte of the bit sequence.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
responsive to determining that the second value matches the first value, selecting a new memory page for storing the first bit sequence.