# US 2021/0342276 A1 · Detecting potentially overlapping input/output queues > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342276 A1 - Document ID: US20210342276A1 - Status: Published application - Kind: A1 - Application number: 16/863,779 - Filed: 2020-04-30 - Published: 2021-11-04 - Earliest claimed: 2020-04-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Kushal S. Patel; Subhojit Roy; Sarvesh S. Patel - Web page: https://patentgrep.com/patent/US20210342276A1 ## CPC - G06F 13/1642: {with request queuing} - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/505: {considering the load} - G06F 13/1668: {Details of memory controller} - G06F 13/20: for access to input/output bus - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer-implemented method, according to one embodiment, includes: receiving an I/O queue creation request, and identifying a first CPU core that can satisfy the I/O queue creation request. A determination is made as to whether the first CPU core already has an I/O queue formed thereon. In response to determining that the first CPU core already has an I/O queue formed thereon, a determination is made as to whether any CPU cores do not already have an I/O queue formed thereon. In response to determining that each CPU core already has an I/O queue formed thereon, the host is informed that satisfying the I/O queue creation request will cause an overlap with existing I/O queues. In response to receiving an indication from the host to satisfy the I/O queue creation request despite the overlap, instructions are sent to use the first CPU core to satisfy the I/O queue creation request. ## Claims ### Claim 1 A computer-implemented method, comprising: receiving an input/output (I/O) queue creation request from a host; identifying a first central processing unit (CPU) core that can be used to satisfy the I/O queue creation request; determining whether the first CPU core already has an I/O queue formed thereon; in response to determining that the first CPU core does already have an I/O queue formed thereon, determining whether any CPU cores do not already have a respective I/O queue formed thereon; in response to determining that each CPU core already has an I/O queue formed thereon, sending one or more instructions to inform the host that satisfying the I/O queue creation request will cause an overlap with one or more existing I/O queues; and in response to receiving an indication from the host to satisfy the I/O queue creation request despite the overlap, sending one or more instructions to use the first CPU core to satisfy the I/O queue creation request. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, comprising: in response to determining that the first CPU core does not already have an I/O queue formed thereon, sending one or more instructions to use the first CPU core to satisfy the I/O queue creation request. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, comprising: in response to determining that at least one CPU core does not have an I/O queue formed thereon, sending one or more instructions to use the at least one CPU core to satisfy the I/O queue creation request. ### Claim 4 (depends on 1) The computer-implemented method of claim 1, comprising: in response to receiving an indication from the host to not satisfy the I/O queue creation request, ignoring the I/O queue creation request. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, comprising: in response to determining that a given CPU core does not already have an I/O queue formed thereon, sending one or more instructions to use the given CPU core to satisfy the I/O queue creation request. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, wherein the operations are performed by a non-volatile memory express (NVMe) storage controller. ### Claim 7 (depends on 6) The computer-implemented method of claim 6, wherein the one or more instructions to use the first CPU core to satisfy the I/O queue creation request are sent to a non-volatile memory express (NVMe) queue manager, wherein in response to receiving the one or more instructions the NVMe queue manager creates an I/O queue on the first CPU core. ### Claim 8 A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to: receive, by the processor, an input/output (I/O) queue creation request from a host; identify, by the processor, a first central processing unit (CPU) core that can be used to satisfy the I/O queue creation request; determine, by the processor, whether the first CPU core already has an I/O queue formed thereon; in response to determining that the first CPU core does already have an I/O queue formed thereon, determine, by the processor, whether any CPU cores do not already have a respective I/O queue formed thereon; in response to determining that each CPU core already has an I/O queue formed thereon, send, by the processor, one or more instructions to inform the host that satisfying the I/O queue creation request will cause an overlap with one or more existing I/O queues; and in response to receiving an indication from the host to satisfy the I/O queue creation request despite the overlap, send, by the processor, one or more instructions to use the first CPU core to satisfy the I/O queue creation request. ### Claim 9 (depends on 8) The computer program product of claim 8, wherein the program instructions are readable and/or executable by the processor to cause the processor to: in response to determining that the first CPU core does not already have an I/O queue formed thereon, send, by the processor, one or more instructions to use the first CPU core to satisfy the I/O queue creation request. ### Claim 10 (depends on 8) The computer program product of claim 8, wherein the program instructions are readable and/or executable by the processor to cause the processor to: in response to determining that at least one CPU core does not have an I/O queue formed thereon, send, by the processor, one or more instructions to use the at least one CPU core to satisfy the I/O queue creation request. ### Claim 11 (depends on 8) The computer program product of claim 8, wherein the program instructions are readable and/or executable by the processor to cause the processor to: in response to receiving an indication from the host to not satisfy the I/O queue creation request, ignore, by the processor, the I/O queue creation request. ### Claim 12 (depends on 8) The computer program product of claim 8, wherein the program instructions are readable and/or executable by the processor to cause the processor to: in response to determining that a given CPU core does not already have an I/O queue formed thereon, send, by the processor, one or more instructions to use the given CPU core to satisfy the I/O queue creation request. ### Claim 13 (depends on 8) The computer program product of claim 8, wherein the operations are performed by a non-volatile memory express (NVMe) storage controller. ### Claim 14 (depends on 13) The computer program product of claim 13, wherein the one or more instructions to use the first CPU core to satisfy the I/O queue creation request are sent to a non-volatile memory express (NVMe) queue manager, wherein in response to receiving the one or more instructions the NVMe queue manager creates an I/O queue on the first CPU core. ### Claim 15 A system, comprising: a processor; and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor, the logic being configured to: receive, by the processor, an input/output (I/O) queue creation request from a host; identify, by the processor, a first central processing unit (CPU) core that can be used to satisfy the I/O queue creation request; determine, by the processor, whether the first CPU core already has an I/O queue formed thereon; in response to determining that the first CPU core does already have an I/O queue formed thereon, determine, by the processor, whether any CPU cores do not already have a respective I/O queue formed thereon; in response to determining that each CPU core already has an I/O queue formed thereon, send, by the processor, one or more instructions to inform the host that satisfying the I/O queue creation request will cause an overlap with one or more existing I/O queues; and in response to receiving an indication from the host to satisfy the I/O queue creation request despite the overlap, send, by the processor, one or more instructions to use the first CPU core to satisfy the I/O queue creation request. ### Claim 16 (depends on 15) The system of claim 15, wherein the logic is configured to: in response to determining that the first CPU core does not already have an I/O queue formed thereon, send, by the processor, one or more instructions to use the first CPU core to satisfy the I/O queue creation request. ### Claim 17 (depends on 15) The system of claim 15, wherein the logic is configured to: in response to determining that at least one CPU core does not have an I/O queue formed thereon, send, by the processor, one or more instructions to use the at least one CPU core to satisfy the I/O queue creation request. ### Claim 18 (depends on 15) The system of claim 15, wherein the logic is configured to: in response to receiving an indication from the host to not satisfy the I/O queue creation request, ignore, by the processor, the I/O queue creation request. ### Claim 19 (depends on 15) The system of claim 15, wherein the logic is configured to: in response to determining that a given CPU core does not already have an I/O queue formed thereon, send, by the processor, one or more instructions to use the given CPU core to satisfy the I/O queue creation request. ### Claim 20 (depends on 15) The system of claim 15, wherein the operations are performed by a non-volatile memory express (NVMe) storage controller, wherein the one or more instructions to use the first CPU core to satisfy the I/O queue creation request are sent to a non-volatile memory express (NVMe) queue manager, wherein in response to receiving the one or more instructions the NVMe queue manager creates an I/O queue on the first CPU core.