# US 2021/0342191 A1 · Dynamic size of static slc cache

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- Number: US 2021/0342191 A1
- Document ID: US20210342191A1
- Status: Published application
- Kind: A1
- Application number: 17/234,225
- Filed: 2021-04-19
- Published: 2021-11-04
- Earliest claimed: 2019-07-12
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Xiangang Luo; Jianmin Huang
- Web page: https://patentgrep.com/patent/US20210342191A1

## CPC

- G06F 9/5016: {the resource being the memory}
- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0649: {Lifecycle management}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 9/30098: {Register arrangements}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2209/5011: Pool
- G06F 2212/1016: Performance improvement
- G06F 2212/1036: Life time enhancement
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7206: Reconfiguration of flash memory system
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Apparatus and methods are disclosed, including using a memory controller to track a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data. A portion of a pool of memory cells of the memory device is reallocated from single level cell (SLC) static cache to SLC dynamic cache storage based at least in part on a value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register, in some examples.

## Claims

### Claim 1

(canceled)

### Claim 2

A storage system comprising:
a memory device including single level cell (SLC) static cache memory cells and SLC dynamic cache memory cells; and
a memory controller configured to perform operations comprising:
tracking a maximum logical saturation over a lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data;
using the tracked logical saturation as an input to a table stored in the memory device; and
determining a portion of a pool of memory cells of the memory device to be reallocated from single level cell (SLC) static cache memory cells to SLC dynamic cache memory cells using the table and based on a current value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register.

### Claim 3 (depends on 2)

The storage system of claim 2, wherein the SLC dynamic storage is configured to be used for an SLC storage mode or a multi-level cell (MLC) storage mode.

### Claim 4 (depends on 3)

The storage system of claim 3, wherein, in MLC storage mode, a memory cell stores three or more bits of data per memory cell.

### Claim 5 (depends on 2)

The storage system of claim 2, wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage includes providing SLC static cache size inversely proportional to the maximum logical saturation.

### Claim 6 (depends on 2)

The storage system of claim 2, wherein at least one of tracking and reallocating are responsive to receiving a write request from a host.

### Claim 7 (depends on 2)

The storage system of claim 2, wherein at least one of tracking and reallocating are performed periodically.

### Claim 8 (depends on 2)

The storage system of claim 2, wherein at least one of tracking and reallocating are performed on a programmable schedule.

### Claim 9

A method comprising:
at a memory controller of a memory device having a lifespan:
during operation of the memory device, tracking a maximum logical saturation over the lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data;
using the tracked logical saturation as an input to a table stored in the memory device; and
determining a portion of a pool of memory cells of the memory device to be reallocated from single level cell (SLC) static cache memory cells to SLC dynamic cache memory cells using the table and based on a current value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register.

### Claim 10 (depends on 9)

The method of claim 9, wherein tracking and reallocating are responsive to receiving a write request from a host.

### Claim 11 (depends on 9)

The method of claim 9, wherein at least one of tracking and reallocating are performed periodically.

### Claim 12 (depends on 9)

The method of claim 9, wherein at least one of tracking and reallocating are performed on a programmable schedule.

### Claim 13 (depends on 9)

The method of claim 9, wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage includes providing SLC static cache size inversely proportional to the maximum logical saturation.

### Claim 14 (depends on 9)

The method of claim 9, wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage does not change combined SLC cache size.

### Claim 15 (depends on 9)

The method of claim 9, wherein a maximum program/erase cycle (PEC) of SLC static cache is 20 to 40 times greater than a maximum PEC of SLC dynamic cache.

### Claim 16

A machine-readable medium, storing instructions, when performed by a controller of a memory device, cause the controller to perform operations during operation of the memory device comprising:
tracking a maximum logical saturation over a lifespan of the memory device, where logical saturation is the percentage of capacity of the memory device written with data;
using the tracked logical saturation as an input to a table stored in the memory device; and
determining a portion of a pool of memory cells of the memory device to be reallocated from single level cell (SLC) static cache memory cells to SLC dynamic cache memory cells using the table and based on a current value of the maximum logical saturation, the reallocating including writing at least one electrical state to a register.

### Claim 17 (depends on 16)

The machine-readable medium of claim 16, wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage includes providing SLC static cache size inversely proportional to the maximum logical saturation.

### Claim 18 (depends on 16)

The machine-readable medium of claim 16, wherein reallocating a portion of a pool of memory cells of the memory device from single level cell (SLC) static cache to SLC dynamic cache storage does not change combined SLC cache size.

### Claim 19 (depends on 16)

The machine-readable medium of claim 16, wherein a maximum program/erase cycle (PEC) of SLC static cache is 20 to 40 times greater than a maximum PEC of SLC dynamic cache.

### Claim 20 (depends on 16)

The machine-readable medium of claim 16, wherein at least one of tracking and reallocating are performed periodically.

### Claim 21 (depends on 16)

The machine-readable medium of claim 16, wherein at least one of tracking and reallocating are performed on a programmable schedule.