# US 2021/0342188 A1 · Harvesting unused resources in a distributed computing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342188 A1 - Document ID: US20210342188A1 - Status: Published application - Kind: A1 - Application number: 16/865,865 - Filed: 2020-05-04 - Published: 2021-11-04 - Earliest claimed: 2020-05-04 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Stanko NOVAKOVIC; Íñigo GOIRI PRESA; Sameh ELNIKETY; Ricardo G. BIANCHINI - Web page: https://patentgrep.com/patent/US20210342188A1 ## CPC - G06F 9/5005: {to service a request} - H04L 63/10: {for controlling access to devices or network resources} - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F 9/5072: {Grid computing} - G06F 12/10: Address translation - G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) - H04L 67/10: in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) - H04L 67/1097: for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] - H04L 67/563: Data redirection of data network streams - H04L 67/565: Conversion or adaptation of application format or content (adding application control or application functional data H04L67/561) - H04L 67/568: Storing data temporarily at an intermediate stage, e.g. caching - G06F 2212/1016: Performance improvement - G06F 2212/1048: Scalability - G06F 2212/151: Emulated environment, e.g. virtual machine - G06F 2212/154: Networked environment - G06F 2212/651: Multi-level translation tables - G06F 2212/657: Virtual address space management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Systems and methods related to harvesting of the unused resources in a distributed computing system are described. An example method, in a system including a host server, having a first instruction set architecture (ISA), and an interface card, having a second ISA is provided. The method includes designating at least one type of resource, associated with the host server for harvesting by compute entities configured for execution using the processor having the second ISA, where the host server is configured to execute compute entities requiring execution by the processor having the first ISA. The method further includes in response to a request for accessing the at least one type of resource by a compute entity, executing on the processor having the second ISA, automatically allowing the compute entity to access the at least one type of resource associated with the host server. ## Claims ### Claim 1 A method in a system including at least one host server and at least one interface card configured to interface with a network or a storage, wherein the at least one host server comprises a processor having a first instruction set architecture (ISA) and the at least one interface card comprises a processor having a second ISA, the method comprising: designating at least one type of resource, associated with the at least one host server for harvesting by compute entities configured for execution using the processor having the second ISA, wherein the at least one host server is configured to execute compute entities requiring execution by the processor having the first ISA; and in response to a request for accessing the at least one type of resource by a compute entity, executing on the processor having the second ISA, automatically allowing the compute entity to access the at least one type of resource associated with the at least one host server. ### Claim 2 (depends on 1) The method of claim 1, wherein the first ISA comprises a complex instruction set computer (CISC) instruction set architecture. ### Claim 3 (depends on 2) The method of claim 2, wherein the second ISA comprises a reduced instruction set computer (RISC) instruction set architecture. ### Claim 4 (depends on 1) The method of claim 1, wherein the at least one resource designated by the host server for harvesting by the compute entities configured for execution using the processor having the second ISA comprises a volatile memory or a non-volatile memory. ### Claim 5 (depends on 1) The method of claim 1, wherein the at least one resource designated by the host server for harvesting by the compute entities configured for execution using the processor having the second ISA comprises an input/output device. ### Claim 6 (depends on 1) The method of claim 1, wherein the compute entity comprises at least one of a virtual machine (VM), a micro-VM, a microservice, or a unikernel for serverless functions. ### Claim 7 (depends on 1) The method of claim 1, wherein the accessing the at least one type of resource by the compute entity comprises performing address translation. ### Claim 8 A method in a system including at least one host server and at least one interface card configured to interface with a network or a storage, wherein the at least one host server comprises a processor having a first instruction set architecture (ISA) and the at least one interface card comprises a processor having a second ISA, the method comprising: the at least one host server designating at least one type of resource, associated with the at least one host server for harvesting by compute entities configured for execution using the processor having the second ISA, wherein the host server is configured to execute virtual machines requiring execution by the processor having the first ISA, and wherein the at least one type of resource includes at least one of a host memory and an input/output (I/O) device; a first hypervisor associated with the at least one host server sharing control information with a second hypervisor associated with the at least one interface card to enable access to a portion of the host memory and a portion of the I/O device; and in response to a request for accessing the at least one type of resource by a compute entity, executing on the processor having the second ISA, automatically allowing the compute entity to access the at least one type of resource associated with the at least one host server. ### Claim 9 (depends on 8) The method of claim 8, wherein the first ISA comprises a complex instruction set computer (CISC) instruction set architecture. ### Claim 10 (depends on 8) The method of claim 8, wherein the second ISA comprises a reduced instruction set computer (RISC) instruction set architecture. ### Claim 11 (depends on 8) The method of claim 8, wherein the host memory comprises a volatile memory or a non-volatile memory. ### Claim 12 (depends on 8) The method of claim 8, wherein the I/O device comprises a storage device or a networking device. ### Claim 13 (depends on 8) The method of claim 8, wherein the compute entity comprises at least one of a virtual machine (VM), a micro-VM, a microservice, or a unikernel for serverless functions. ### Claim 14 (depends on 8) The method of claim 8, wherein the accessing the at least one type of resource by the compute entity comprises performing address translation. ### Claim 15 (depends on 8) The method of claim 8, wherein the control information comprises information concerning mapping of memory pages associated with the at least one host server. ### Claim 16 A distributed computing system comprising: a host server comprising a processor having a first instruction set architecture (ISA), wherein the host server is configured to service compute entities corresponding to at least one tenant, and wherein each of the compute entities is required to execute using the processor having the first ISA; an interlace card, coupled to the host server, comprising a processor having a second ISA; and a system configured to: allow designation of at least one type of resource, associated with the host server for harvesting by compute entities configured for execution using the processor having the second ISA, allow sharing of control information between a first hypervisor associated with the host sever and a second hypervisor with the interlace card, and in response to a request for accessing the at least one type of resource by a compute entity, executing on the processor having the second ISA, automatically allow the compute entity to access the at least one type of resource associated with the at least one host server. ### Claim 17 (depends on 16) The distributed computing system of claim 16, wherein the first ISA comprises a complex instruction set computer (CISC) instruction set architecture and wherein the second ISA comprises a reduced instruction set computer (RISC) instruction set architecture. ### Claim 18 (depends on 17) The distributed computing system of claim 17, wherein the at least one resource designated by the host server for harvesting by the virtual machines configured for execution using the processor having the second ISA comprises a volatile memory, a non-volatile memory, or an input/output device. ### Claim 19 (depends on 18) The distributed computing system of claim 18, wherein the compute entity comprises at least one of a virtual machine (VM), a micro-VM, a microservice, or a unikernel for serverless functions. ### Claim 20 (depends on 19) The distributed computing system of claim 19, wherein the control information includes information concerning mapping of memory pages associated with the at least one host server.