# US 2021/0342160 A1 · Processor and method for controlling the processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342160 A1 - Document ID: US20210342160A1 - Status: Published application - Kind: A1 - Application number: 17/375,574 - Filed: 2021-07-14 - Published: 2021-11-04 - Earliest claimed: 2019-03-04 - Assignees: Panasonic Intellectual Property Management Co., Ltd. - Applicants: Panasonic Intellectual Property Management Co., Ltd. - Inventors: Yoshiteru HAYASHI - Web page: https://patentgrep.com/patent/US20210342160A1 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30109: {having multiple operands in a single register} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor performs, in accordance with a single instruction, multiplication processing and comparison processing. The multiplication processing includes obtaining a multiplication result by multiplying together a first data element and a first value. The comparison processing includes comparing the multiplication result with a second data element. The first data element is stored in a first register, the second data element is stored in a second register, and the first value is stored in a third register. ## Claims ### Claim 1 A processor configured to perform, in accordance with a single instruction, multiplication processing and comparison processing, the multiplication processing including obtaining a multiplication result by multiplying together a first data element and a first value, the comparison processing including comparing the multiplication result with a second data element, the first data element being stored in a first register, the second data element being stored in a second register, the first value being stored in a third register. ### Claim 2 (depends on 1) The processor of claim 1, wherein the processor is configured to further perform, in accordance with the single instruction, replacement processing including replacing, based on a result of the comparison processing, a third data element with a second value, the third data element being stored in a fourth register, the second value being further stored in the third register. ### Claim 3 (depends on 2) The processor of claim 2, wherein multiple sets are stored in the third register, each of the multiple sets includes the first value and the second value, the multiple sets are stored in mutually different storage areas in the third register, the single instruction includes a plurality of instruction mnemonics, and each of the plurality of instruction mnemonics causes the processor to read the first value and the second value of an associated one of the multiple sets that are stored in the mutually different storage areas. ### Claim 4 (depends on 2) The processor of claim 2, wherein a bit width of each of the first data element and the second data element is different from a bit width of the third data element. ### Claim 5 (depends on 2) The processor of claim 2, wherein the processor includes the first register, the second register, the third register, and the fourth register, register numbers are assigned as identification numbers to the first register, the second register, the third register, and the fourth register, and the respective register numbers of at least one register and another register which are selected from the group consisting of the first register, the second register, the third register, and the fourth register are serial numbers. ### Claim 6 (depends on 2) The processor of claim 2, wherein the processor includes the first register, the second register, the third register, and the fourth register, the register number of at least one register selected from the group consisting of the first register, the second register, the third register, and the fourth register is fixed. ### Claim 7 (depends on 2) The processor of claim 2, wherein a plurality of the first data elements are stored in the first register, a plurality of the second data elements are stored in the second register, a plurality of the third data elements are stored in the fourth register, the multiplication processing includes obtaining a plurality of the multiplication results by multiplying the plurality of the first data elements and the first value together, the plurality of the multiplication results being associated with the plurality of the second data elements, the comparison processing includes obtaining a plurality of comparison results by comparing the plurality of the second data elements with associated ones of the plurality of the multiplication results, the plurality of comparison results being associated with the plurality of the third data elements, and the replacement processing includes replacing the plurality of the third data elements stored in the fourth register with the second value based on associated ones of the plurality of comparison results. ### Claim 8 (depends on 7) The processor of claim 7, wherein multiple sets are stored in the third register, each of the multiple sets includes the first value and the second value, the multiple sets are arranged in line, the processor is configured to read, in accordance with the single instruction, the first value and the second value of a set stored in a predetermined area of the third register as the first value for use in the multiplication processing and the second value for use in the replacement processing, respectively, and the processor is configured to further perform, in accordance with the single instruction, shift processing including shifting, in one direction, the multiple sets stored in the third register such that a set stored in an area adjacent to the predetermined area moves to the predetermined area. ### Claim 9 (depends on 8) The processor of claim 8, wherein when the multiple sets are called a first plurality of sets, and the one direction is called a first shift direction, a second plurality of sets are stored in a fifth register, each of the second plurality of sets includes the first value and the second value, the second plurality of sets are arranged in line, and the shift processing includes the processing of shifting, by one set, the second plurality of sets in a second shift direction and moving a second set, located at one end in the second shift direction, out of the second plurality of sets to a specified area in the third register, the specified area being adjacent to a first set, located at one end in a direction opposite from the first shift direction, out of the first plurality of sets. ### Claim 10 (depends on 1) The processor of claim 1, wherein the first data element and the second data element are mutually correlated data elements. ### Claim 11 (depends on 1) The processor of claim 1, wherein the single instruction further causes the processor to perform shift processing including shifting, by a predetermined number of bits, the second data element stored in the second register. ### Claim 12 (depends on 11) The processor of claim 11, wherein the single instruction has a variable replaceable with the predetermined number of bits to shift entered. ### Claim 13 (depends on 1) The processor of claim 1, comprising the third register, wherein the third register is a general-purpose register. ### Claim 14 (depends on 4) The processor of claim 4, wherein the third data element is stored in a storage area that forms a least significant half of the fourth register. ### Claim 15 (depends on 4) The processor of claim 4, wherein the third data element is stored in a storage area that forms a most significant half of the fourth register. ### Claim 16 (depends on 4) The processor of claim 4, wherein a bit width of each of the first data element and the second data element is less than a bit width of the third data element. ### Claim 17 (depends on 8) The processor of claim 8, wherein all of the multiple sets, each including the first value and the second value, are stored in the third register. ### Claim 18 (depends on 1, 2) The processor of claim 1 claim 2, wherein an instruction code of the single instruction describes an operation code that defines an instruction and a register number that specifies a register, and a register number of at least one of the first register, the second register, the third register, or the fourth register is in series with a register number of another one of the first, second, third, or fourth register. ### Claim 19 (depends on 1, 2) The processor of claim 1 claim 2, wherein an instruction code of the single instruction describes an operation code that defines an instruction and a register number that specifies a register, and a register number of at least one of the first register, the second register, the third register, or the fourth register is fixed. ### Claim 20 A method for controlling a processor, the method comprising performing, in accordance with a single instruction, multiplication processing and comparison processing, the multiplication processing including obtaining a multiplication result by multiplying together a first data element and a first value, the comparison processing including comparing the multiplication result with a second data element, the first data element being stored in a first register, the second data element being stored in a second register, the first value being stored in a third register.