# US 2021/0342159 A1 · Method for implementing a line speed interconnect structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342159 A1 - Document ID: US20210342159A1 - Status: Published application - Kind: A1 - Application number: 17/226,885 - Filed: 2021-04-09 - Published: 2021-11-04 - Earliest claimed: 2013-03-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Mohammad ABDALLAH - Web page: https://patentgrep.com/patent/US20210342159A1 ## CPC - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F 9/3004: {to perform operations on memory} - G06F 9/3853: {of compound instructions} - G06F 9/462: {with multiple register sets} - G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) - G06F 12/0853: Cache with multiport tag or data arrays - G06F 12/0886: Variable-length word access - G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 ) - G06F 15/17318: {Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all} - H04L 12/28: characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] (wireless communication networks H04W {; arrangements for dividing the transmission path H04W40/00}) - H04L 49/1523: {Parallel switch fabric planes} - G06F 2212/1041: Resource optimization - G06F 2212/1056: Simplification - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed. ## Claims ### Claim 1 A method for pipeline speed computer instruction processing, comprising: receiving a plurality of computer instructions; performing a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions; performing combining and splitting of the plurality of computer instructions by a second stage; and forwarding the plurality of computer instructions to a next processing stage in the pipeline at pipeline speed. ### Claim 2 (depends on 1) The method of claim 1, wherein the first stage performs position shuffling, pairing, and splitting of the computer instructions based on a destination of each of the plurality of computer instructions. ### Claim 3 (depends on 1) The method of claim 1, wherein the combining combines microinstructions of the plurality of computer instructions that have a same destination next stage of the pipeline. ### Claim 4 (depends on 1) The method of claim 1, wherein the splitting splits computer instructions that have a different destination next stage of the pipeline. ### Claim 5 (depends on 1) The method of claim 1, wherein the plurality of computer instructions are each composed of at least one microinstruction. ### Claim 6 (depends on 1) The method of claim 1, wherein computer instructions that exceed a given number of microinstructions are split into at least two computer instructions. ### Claim 7 A processor device, comprising: a scheduler to select from a plurality of computer instructions for dispatch; a pipeline to process the computer instructions; and a remapper coupled to the scheduler and pipeline, the remapper configured to receive the plurality of computer instructions, perform a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions, perform combining and splitting of the plurality of computer instructions by a second stage, and forwarding the plurality of computer instructions to a next processing stage in the pipeline at pipeline speed. ### Claim 8 (depends on 7) The processor of claim 7, wherein the first stage performs position shuffling, pairing, and splitting of the computer instructions based on a destination of each of the plurality of computer instructions. ### Claim 9 (depends on 7) The processor of claim 7, wherein the combining combines microinstructions of the plurality of computer instructions that have a same destination next stage of the pipeline. ### Claim 10 (depends on 7) The processor of claim 7, wherein the splitting splits computer instructions that have a different destination next stage of the pipeline. ### Claim 11 (depends on 7) The processor of claim 7, wherein the plurality of computer instructions are each composed of at least one microinstruction. ### Claim 12 (depends on 7) The processor of claim 7, wherein computer instructions that exceed a given number of microinstructions are split into at least two computer instructions. ### Claim 13 A computer system, comprising: a main memory; and a processor coupled to the main memory, the processor including a remapper, the remapper configured to receive a plurality of computer instructions, perform a pre-sorting of the plurality of computer instructions by a first stage to order the plurality of computer instructions, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of computer instructions in parallel to map the plurality of computer instructions from a first position to a second position based on a number of microoperations in each of the plurality of computer instructions, perform combining and splitting of the plurality of computer instructions by a second stage, and forwarding the plurality of computer instructions to a next processing stage in a pipeline at pipeline speed. ### Claim 14 (depends on 13) The computer system of claim 13, wherein the first stage of the remapper performs position shuffling, pairing, and splitting of the computer instructions based on a destination of each of the plurality of computer instructions. ### Claim 15 (depends on 13) The computer system of claim 13, wherein the combining combines microoperations of the plurality of computer instructions that have a same destination next stage of the pipeline. ### Claim 16 (depends on 13) The computer system of claim 13, wherein the splitting splits computer instructions that have a different destination next stage of the pipeline. ### Claim 17 (depends on 13) The computer system of claim 13, wherein the plurality of computer instructions are each composed of at least one microoperation. ### Claim 18 (depends on 13) The computer system of claim 13, wherein computer instructions that exceed a given number of microoperations are split into at least two computer instructions.