# US 2021/0342152 A1 · Handling load-exclusive instructions in apparatus having support for transactional memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342152 A1 - Document ID: US20210342152A1 - Status: Published application - Kind: A1 - Application number: 17/255,001 - Filed: 2019-05-09 - Published: 2021-11-04 - Earliest claimed: 2018-06-25 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Matthew James HORSNELL; Grigorios MAGKLIS; Richard Roy GRISENTHWAITE; Nathan Yong Seng CHONG - Web page: https://patentgrep.com/patent/US20210342152A1 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/3004: {to perform operations on memory} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/3842: {Speculative instruction execution} - G06F 9/38585: {with result invalidation, e.g. nullification} - G06F 9/528: {by using speculative mechanisms} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread. ## Claims ### Claim 1 An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing circuitry is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transaction memory support circuitry comprising conflict detection circuitry to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which: in response to a load-exclusive instruction specifying a given address, the processing circuitry is configured to set an exclusive monitor indication for the given address; in response to a store-exclusive instruction specifying the given address, the processing circuitry is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set; in response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, the processing circuitry is configured to trigger clearing of any exclusive monitor indication previously set for the load target address; and in response to said load-exclusive instruction, at least one of the processing circuitry and the transactional memory support circuitry is configured to trigger an abort of a transaction for which the given address is specified as one of the working set of addresses. ### Claim 2 (depends on 1) The apparatus according to claim 1, in which the processing circuitry comprises a plurality of processing elements capable of parallel execution of multiple threads of processing. ### Claim 3 (depends on 2) The apparatus according to claim 2, in which in response to the load-exclusive instruction being executed on a given processing element of the plurality of processing elements, the given processing element is configured to trigger transmission of a message to at least one other processing element, the message indicating that the exclusive monitor indication was set for said given address. ### Claim 4 (depends on 2) The apparatus according to claim 2, in which in response to the predetermined type of load instruction being executed on a given processing element of the plurality of processing elements, the given processing element is configured to trigger transmission of a message to at least one other processing element of the plurality of processing elements, the message indicating that any exclusive monitor indication previously set by said at least one other processing element for the load target address should be cleared. ### Claim 5 (depends on 1) The apparatus according to claim 1, in which in response to the predetermined type of load instruction executed within the given transaction, the processing circuitry is configured to add the load target address to the working set of addresses for the given transaction. ### Claim 6 (depends on 1) The apparatus according to claim 1, in which in response to a second type of load instruction specifying a load target address, which is executed within the given transaction, the processing circuitry is configured to retain any previously set exclusive monitor indication for the load target address. ### Claim 7 (depends on 1) The apparatus according to claim 1, in which the processing circuitry is configured to support a given thread speculatively executing a load instruction for loading a data value from a target address before the processing circuitry has resolved whether a lock variable for controlling exclusive access to said target address has been successfully claimed by the given thread. ### Claim 8 (depends on 1) The apparatus according to claim 1, comprising exclusive monitor circuitry to trigger clearing of the exclusive monitor indication set for the given address in response to detecting one of: the processing circuitry executing a load-exclusive instruction specifying the given address or another address; the processing circuitry executing said predetermined type of load instruction specifying the given address as the load target address; and a store operation to store data to a memory location corresponding to the given address. ### Claim 9 (depends on 1) The apparatus according to claim 1, in which the transaction memory support circuitry also comprises at least one of: speculative result storage circuitry to store results of speculatively executed instructions for at least one transaction; and restoration state storage circuitry to store state captured in response to the transaction start instruction to be restored on aborting the transaction. ### Claim 10 A data processing method comprising: in response to a load-exclusive instruction specifying a given address, setting an exclusive monitor indication for the given address; in response to a store-exclusive instruction specifying the given address, returning a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set; in response to a predetermined type of load instruction specifying a load target address, which is executed within a transaction, clearing any exclusive monitor indication previously set for the load target address, the transaction comprising instructions of a given thread executed speculatively between a transaction start instruction and a transaction end instruction, for which commitment of results of the speculatively executed instructions is prevented until the transaction end instruction is reached, where the transaction is to be aborted in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; and in response to said load-exclusive instruction, triggering an abort of a transaction for which the given address is specified as one of the working set of addresses. ### Claim 11 A computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of threads of data processing; the computer program comprising: processing program logic to process threads of data processing; and transactional memory program logic to support execution of a transaction within a thread processed by the processing program logic, the transaction comprising instructions of the thread executed speculatively between a transaction start instruction and a transaction end instruction, for which the processing program logic is configured to prevent commitment of results of the speculatively executed instructions until the transaction end instruction is reached, the transaction memory program logic comprising conflict detection program logic to trigger an abort of the transaction in response to detecting a conflicting access from another thread to one of a working set of addresses tracked for the transaction; in which: in response to a load-exclusive instruction specifying a given address, the processing program logic is configured to set an exclusive monitor indication for the given address; in response to a store-exclusive instruction specifying the given address, the processing program logic is configured to return a store-exclusive fail indication when the given address no longer has the exclusive monitor indication set; in response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, the processing program logic is configured to trigger clearing of any exclusive monitor indication previously set for the load target address; and in response to said load-exclusive instruction, at least one of the processing program logic and the transactional memory program logic is configured to trigger an abort of a transaction for which the given address is specified as one of the working set of addresses. ### Claim 12 An interconnect comprising: a plurality of interfaces to exchange messages with a plurality of processing elements; and control circuitry configured to manage coherency between the plurality of processing elements; in which: in response to an exclusive monitor setting message from a given processing element indicating setting of an exclusive monitor indication associated with a given address for tracking exclusive access to the given address, the control circuitry is configured to trigger the interfaces to transmit the exclusive monitor setting message to at least one other processing element; and in response to a predetermined type of read request received from a first processing element requesting return of a read data value associated with a target address specified by the first type of read request, the control circuitry is configured to trigger the interfaces to transmit an exclusive monitor cancelling message to at least one other processing element to trigger cancellation of any exclusive monitor indication associated with the target address.