# US 2021/0342134 A1 · Code prefetch instruction

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- Number: US 2021/0342134 A1
- Document ID: US20210342134A1
- Status: Published application
- Kind: A1
- Application number: 17/033,751
- Filed: 2020-09-26
- Published: 2021-11-04
- Earliest claimed: 2020-04-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ahmad Yasin; Lihu Rappoport; Jared W. Stark; Jeffrey Baxter; Israel Diamand; Pavel Fridman; Ibrahim Hur; Nir Tell
- Web page: https://patentgrep.com/patent/US20210342134A1

## CPC

- G06F 8/4442: {Reducing the number of cache misses; Data prefetching (cache prefetching G06F12/0862)}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/3802: {Instruction prefetching}
- G06F 12/0862: with prefetch
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of apparatuses, methods, and systems for code prefetching are described. In an embodiment, an apparatus includes an instruction decoder, load circuitry, and execution circuitry. The instruction decoder is to decode a code prefetch instruction. The code prefetch instruction is to specify a first instruction to be prefetched. The load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction. The execution circuitry is to execute the first instruction at a fetch stage of a pipeline.

## Claims

### Claim 1

An apparatus comprising:
an instruction decoder to decode a code prefetch instruction, wherein the code prefetch instruction is to specify a first instruction to be prefetched;
load circuitry to prefetch the first instruction in response to the decoded code prefetch instruction; and
execution circuitry to execute the first instruction at a fetch stage of a pipeline.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first instruction is in program code stored in a memory.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the code prefetch instruction is to specify an address of the first instruction.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the code prefetch instruction is to specify the address of the first instruction in a displacement field.

### Claim 5 (depends on 3)

The apparatus of claim 3, wherein the code prefetch instruction is to specify the address of the first instruction in an immediate field.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein the code prefetch instruction is to specify the address as an offset.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the code prefetch instruction is to specify the address as an offset from an instruction pointer.

### Claim 8 (depends on 2)

The apparatus of claim 2, wherein a span of the program code to be prefetched is to be specified by a parameter of the code prefetch instruction.

### Claim 9 (depends on 2)

The apparatus of claim 2, wherein the span is to be a multiple of a size of a cache line.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the code prefetch instruction is to provide a hint to the apparatus, wherein the processor may ignore the hint.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein a location to which the first instruction is to be prefetched is specified by a parameter of the code prefetch instruction.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein prefetch of the first instruction may be conditional.

### Claim 13 (depends on 1)

The apparatus of claim 1, further comprising performance monitoring hardware, wherein the performance monitoring hardware may be configured to provide information regarding an event related to performance of software using the code prefetching instruction.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein the event is related to fetch latency.

### Claim 15

A method comprising:
decoding a code prefetch instruction, wherein the code prefetch instruction is to specify a first instruction to be prefetched;
in response to the decoded code prefetch instruction, prefetching the first instruction; and
executing the first instruction at a fetch stage of a pipeline.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first instruction is in program code stored in the memory.

### Claim 17 (depends on 16)

The method of claim 16, wherein the code prefetch instruction is to specify an address of the first instruction.

### Claim 18 (depends on 16)

The method of claim 16, wherein a span of the program code to be prefetched is to be specified by a parameter of the code prefetch instruction.

### Claim 19

A system comprising:
a memory;
a processor including:
an instruction decoder to decode a code prefetch instruction, wherein the code prefetch instruction is to specify a first instruction to be prefetched;
load circuitry to prefetch the first instruction from the memory in response to the decoded code prefetch instruction; and
execution circuitry to execute the first instruction at a fetch stage of a pipeline.

### Claim 20 (depends on 19)

The system of claim 19, wherein the first instruction is in program code stored in the memory.