# US 2021/0342121 A1 · Low area multiply and accumulate unit

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- Number: US 2021/0342121 A1
- Document ID: US20210342121A1
- Status: Published application
- Kind: A1
- Application number: 16/862,722
- Filed: 2020-04-30
- Published: 2021-11-04
- Earliest claimed: 2020-04-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Sudipto Chakraborty; Rajiv Joshi
- Web page: https://patentgrep.com/patent/US20210342121A1

## CPC

- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06G 7/16: for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06F 2207/4814: Non-logic devices, e.g. operational amplifiers
- G06N 3/063: using electronic means
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

An improved electronic mixed mode multiplier and accumulate circuit for artificial intelligence and computing system applications that perform vector-vector, vector-matrix and other multiply-accumulate computations. The circuit is provided is a high resolution, high linearity, low area, low power multiply—accumulate (MAC) unit to interface with a memory device for storing computation output results. The MAC unit uses a less number of current carrying elements resulting in much lower integrated circuit area, and provides a tight matching between the current elements thus preserving inherent linearity requirements due to current mode operation. Further the MAC performs current scaling using switches and current division where the current switches occupy minimum size transistors requiring a small area to implement that renders it compatible with MRAM such as a magnetic tunnel junction device. The MAC is hierarchically extended for increased number of bits to provide a delay implementation using orthogonal vector and current addition.

## Claims

### Claim 1

An electronic device comprising:
a plurality of current carrying elements, each current carrying element of a uniform size to each provide a matched current output;
one or more current splitters, a current splitter coupled to one current carrying element of said plurality for receiving a matched current output from its coupled current carrying element, each current splitter comprising a series of weighted switching transistor structures, each respective weighted switching transistor of the series configured for dividing current received from its coupled current carrying element according to a weighting scheme, a respective weighted switching transistor of the series further receiving a respective bit of an input digital word to be multiplied, a respective bit controlling a current flow at a respective path of that respective switching transistor from the input current carrying element; and
an output conductor connected to an output of each weighted switching transistor of the series for accumulating each current flow output of a respective path of the series of weighted switching transistors of a current splitter as controlled by the respective input digital word bits, the accumulated current flow output representing an analog current representation of the first input digital word.

### Claim 2 (depends on 1)

The electronic device of claim 1, further comprising; a non-volatile memory storage element or volatile memory storage element coupled to output conductor for receiving and storing said analog current representation of the input digital word.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein said memory storage element is one of an MRAM, PCM or ReRAM memory storage cell.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the weighting scheme is a binary weighting scheme such that each successive switching transistor of a current splitter is sized to provide divide input current according to 2k, where k is a whole number representing a bit position of an input word being multiplied.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the weighting scheme is a different radix other than binary weighting.

### Claim 6 (depends on 1)

The electronic device of claim 1, comprising first and second current splitters coupled with respective first and second matched current carrying elements, a first current splitter having a first series of weighted switching transistor structures receiving a first input digital word to be multiplied and a second current splitter having a second series of weighted switching transistor structures receiving a second input digital word to be multiplied,
each respective weighted switching transistor of the first series configured for dividing current received from its coupled current carrying element according to the weighting scheme to provide a first multiplication path current flow output of said first current splitter, and each respective weighted switching transistor of the second series configured for dividing current received from its coupled current carrying element according to the weighting scheme to provide a second multiplication path current flow output of said second current splitter, and
the output conductor connected to sum the first multiplication path current flow output and said second multiplication path current flow output of each respective first and second current splitter.

### Claim 7 (depends on 6)

The electronic device of claim 6, wherein said first input digital word to be multiplied and said second input digital word to be multiplied comprise are of a same bit resolution or different bit resolutions.

### Claim 8 (depends on 4)

The electronic device of claim 4, wherein an input digital word is programmed to receive a N-bit resolution digital word, said electronic device configured with a quantity 2U matched current carrying elements, wherein a number of weighted switching transistor structures in a series of a current splitter includes a number K of binary weighted switches, where U+K=N.

### Claim 9 (depends on 8)

The electronic device of claim 8, wherein K<N, said device further comprising: a control device receiving a quantity N-K excess digital bits of said received input digital word, said controller responding to said excess digital bits for selecting and activating additional one or more said 2U matched current carrying elements.

### Claim 10 (depends on 9)

The electronic device of claim 9, further comprising a switch device associated with each said 2U matched current carrying elements, an associated switch device receiving a control signal for activating or de-activating one or more said 2U matched current carrying elements responsive to said excess digital bits.

### Claim 11

An electronic device comprising:
a plurality of current carrying elements, each current carrying element of a uniform size to each provide a matched current output;
a first current splitter and a second current splitter each first and second current splitter coupled with respective first matched current carrying element and a second matched current carrying element, the first and second current splitters comprising a first hierarchy current scaling network, the first current splitter having a first series of weighted switching transistor structures receiving a first input digital word to be multiplied and the second current splitter having a second series of weighted switching transistor structures receiving a second input digital word to be multiplied,
each respective weighted switching transistor of the first series configured for dividing current received from its coupled current carrying element according to the weighting scheme to provide a first multiplication path current flow output of said first current splitter, and each respective weighted switching transistor of the second series configured for dividing current received from its coupled current carrying element according to the weighting scheme to provide a second multiplication path current flow output of said second current splitter;
a first output conductor receiving the first multiplication path current flow output;
a second output conductor receiving the second multiplication path current flow output; and
a second hierarchy current scaling network connected to the first hierarchy current scaling network, said second hierarchy current scaling network comprising:
third and fourth current splitters, the third current splitter coupled with said first output conductor, and said fourth current splitter coupled with said second output conductor.

### Claim 12 (depends on 11)

The electronic device of claim 11, wherein the third current splitter of said second hierarchy current scaling network comprises:
a third first series of weighted switching transistor structures receiving a third input digital word to be multiplied, and the fourth current splitter of said second hierarchy current scaling network comprises:
a fourth first series of weighted switching transistor structures receiving a third input digital word to be multiplied,
wherein said first multiplication path current flow output at said first output conductor is further divided according to the received third input digital input word, and said second multiplication path current flow output at said second output conductor is further divided according to the received fourth digital input word.

### Claim 13 (depends on 12)

The electronic device of claim 12, further comprising: a further output conductor, said further output conductor providing a summed analog output current comprising:
a third multiplication path current flow output of said third current splitter resulting from a further dividing of said first multiplication path current flow output according to the received third input digital input word, and
a fourth multiplication path current flow output of said fourth current splitter resulting from a further dividing of said second multiplication path current flow output according to the received fourth input digital input word; and
a memory storage element coupled to the further output conductor for receiving and storing said summed analog output current.

### Claim 14 (depends on 13)

The electronic device of claim 13, wherein the weighting scheme is one of:
a binary weighting scheme such that each successive switching transistor of a respective first current splitter, second current splitter, third current splitter and fourth current splitter is sized to provide divide input current according to 2k, where k is a whole number representing a bit position of an input word being multiplied; or
is a different radix weighting scheme that is other than binary weighting

### Claim 15 (depends on 13)

The electronic device of claim 13, wherein the third input digital word at said third current splitter is of a same or different bit resolution as said first input digital word at said first current splitter; and said fourth input digital word at said fourth current splitter is of a same or different bit resolution as said second input digital word at said second current splitter.

### Claim 16 (depends on 11)

The electronic device of claim 11, wherein the second digital word input to said second current splitter of said first hierarchy current scaling network is a delayed version of said first input digital word to said first current splitter of said first hierarchy current scaling network,
wherein the first digital word input and second digital word input is obtained from a data sampled according to a clock frequency, said first input digital word comprising a sampled sequence at a rate according to a fundamental clock frequency and said second input digital word comprising a sampled sequence delayed by a quarter phase relative to said fundamental clock frequency.

### Claim 17 (depends on 15)

The electronic device of claim 15, wherein the first digital word input and second digital word input at respective first and second current splitters of said first hierarchy current scaling network represent a first vector quantity to be multiplied; and
the third digital word input and fourth digital word input at respective third and fourth current splitters of said second hierarchy current scaling network represent a second vector quantity to be multiplied, wherein the summed analog output current at said further output conductor comprising an analog current representation of a multiplication of said first vector and second vector quantities.

### Claim 18 (depends on 17)

The electronic device of claim 17, wherein one or more plurality of current carrying elements are configured to provide a respective weight value for use in a multiplication of said first vector and second vector quantities.

### Claim 19 (depends on 17)

The electronic device of claim 17, wherein
said first and second current splitters receiving respective first digital word input and second digital word inputs at said first hierarchy current scaling network receive current from a first subset of a first total amount of first current carrying elements sourcing current to said first and second current splitters, and
said third and fourth current splitters receiving said third digital word input and fourth digital word inputs at said second hierarchy current scaling network receive current from a second subset of a second total amount of second current carrying elements sourcing current to said third and fourth current splitters, and
a ratio comprising a number of said second subset of said second amount of current carrying elements over a number of said first subset of said first amount of current carrying elements represent a phase shift angle.

### Claim 20 (depends on 19)

The electronic device of claim 19, wherein a ratio of a number of said first subset of first current carrying elements over a number of said first total amount of first current carrying elements provide a first coefficient value for a trigonometric sin θ vector represented by first and second digital input words; and
a ratio of a number of said second subset of second current carrying elements over a number of said second total amount of second current carrying elements provide a second coefficient value for a trigonometric cosin θ vector represented by third and fourth digital input words.