# US 2021/0342102 A1 · Signal processing apparatus, method, program, and recording medium > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0342102 A1 - Document ID: US20210342102A1 - Status: Published application - Kind: A1 - Application number: 17/057,082 - Filed: 2019-05-21 - Published: 2021-11-04 - Earliest claimed: 2018-05-22 - Assignees: NEC Corporation - Applicants: NEC Corporation - Inventors: Atsufumi SHIBAYAMA; Hajime YAMAGIAWA - Web page: https://patentgrep.com/patent/US20210342102A1 ## CPC - G06F 17/142: {Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm} - G06F 7/50: Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A signal processing apparatus includes a storage processing part that performs storage processing on data represented in a second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted, and an operation processing part that performs operation processing on at least any one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format. ## Claims ### Claim 1 A signal processing apparatus, comprising: a storage processing part that performs storage processing on data represented in a second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted; and an operation processing part that performs operation processing on at least one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format. ### Claim 2 (depends on 1) The signal processing apparatus according to claim 1, wherein the compensation processing adds a value one to M bits from a least significant bit, where M is a positive integer and not more than N which is a predetermined positive integer, in data of N bits when the data of N bits represented in the second representation format is of a negative value. ### Claim 3 (depends on 1) The signal processing apparatus according to claim 1, wherein the operation processing part performs, when an operation to be processed is a multiplication or a division, the operation processing on any of data obtained by applying the compensation processing to data represented in the second representation format, while the operation processing part performs, when an operation to be processed is an addition or a subtraction, the operation processing on data represented in a two's complement representation. ### Claim 4 (depends on 1) The signal processing apparatus according to claim 1, wherein the storage processing part comprises: at least one selected from: a configuration including a storage circuit; and a configuration including the storage circuit and at least one of a first conversion part or a second conversion part, wherein the first conversion part receives data represented in a two's complement representation to convert the received data from the two's complement representation to the second representation format, wherein the storage circuit performs storage processing on the data in the second representation format for output, and wherein the second conversion part receives the data represented in the second representation format outputted from the storage circuit to convert the received data into a two's complement representation for output. ### Claim 5 (depends on 1) The signal processing apparatus according to claim 1, wherein the operation processing part comprises: at least one selected from: a configuration including a first operation circuit; a configuration including a compensation circuit and a second operation circuit; and a configuration including the compensation circuit, the second operation circuit, and at least one of a first conversion part or a second conversion part, wherein the first operation circuit receives data represented in a two's complement representation to perform operation processing on the data represented in the two's complement representation, wherein the first conversion part receives data represented in a two's complement representation to converts the received data from the two's complement representation to the second representation format, wherein the compensation circuit performs the compensation processing on data represented in the second representation format, wherein the second operation circuit receives data having the compensation processing applied thereto by the compensation circuit to perform operation processing on the data having the compensation processing applied thereto, and wherein the second conversion part receives data represented in the second representation format to convert the received data to a two's complement representation for output. ### Claim 6 (depends on 5) The signal processing apparatus according to claim 5, wherein the second operation circuit comprises: a sign operation circuit that outputs a result of an operation performed on one or more sign bits of one or more individual items of data of operation target in the second representation format with the compensation processing applied thereto, as a sign bit; and an unsigned operation circuit that performs an operation on one or more magnitude parts other than the one or more sign bits of the one or more individual items of data of operation target represented in the second representation format with the compensation processing applied thereto to for-output a result of the operation as a magnitude part. ### Claim 7 (depends on 4) The signal processing apparatus according to claim 4, wherein the first conversion part and the second conversion part each output a most significant bit of the received data as it is as a most significant bit, and, as for each bit other than the most significant bit of the received data, output a result of taking exclusive OR with the most significant bit. ### Claim 8 (depends on 1) The signal processing apparatus according to claim 1, wherein signal processing apparatus performs a fast Fourier transform or an inverse fast Fourier transform using both a two's complement representation and the second representation format as data representation formats, wherein the operation processing part comprises: a butterfly operation processing part that performs butterfly operation processing; and a twiddle factor multiplication processing part that performs twiddle factor multiplication processing, and wherein the storage processing part comprises: a data reordering processing part that rearranges an order of a plurality of data, wherein the butterfly operation processing part performs the butterfly operation processing on data represented in the two's complement representation, wherein the twiddle factor multiplication processing part performs operation processing on data obtained by applying compensation processing to data represented in the second representation format, for multiplication processing, the twiddle factor multiplication processing part performing operation processing on data represented in a two's complement representation, for addition processing, and wherein the data reordering processing part performs storage processing on data represented in the second representation format. ### Claim 9 (depends on 8) The signal processing apparatus according to claim 8, wherein the data reordering processing part comprises: a first conversion part that receives data represented in a two's complement representation to convert the data received into the second representation format; and a second conversion part that receives data represented in the second representation format to convert the data received into a two's complement representation, wherein the first conversion part converts the received data represented in a two's complement representation into the second representation format to perform data reordering processing on the data converted, and wherein the second conversion part converts data represented in the second representation format with the data reordering processing applied into a two's complement representation for output. ### Claim 10 (depends on 8) The signal processing apparatus according to claim 8, wherein the first conversion part and the second conversion part output a most significant bit of the received data as it is, and as for each bit other than the most significant bit, output a result of taking exclusive OR of the each bit and the most significant bit. ### Claim 11 A signal processing method, comprising: performing storage processing on data represented in a second representation format that is different from a two's complement representation; and performing operation processing on at least one of data represented in a two's complement representation or data obtained by applying compensation processing to data represented in the second representation format, wherein, when a value of the data is positive or zero, the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted. ### Claim 12 (depends on 11) The signal processing method according to claim 11, comprising in the compensation processing, adding a value one to M bits from a least significant bit (where M is a positive integer and not more than N) in data of N bits (where N is a predetermined positive integer) when the data of N bits (N being a positive integer) represented in the second representation format has a negative value. ### Claim 13 (depends on 11) The signal processing method according to claim 11, comprising in the operation processing, performing, when an operation to be processed is a multiplication or a division, the operation processing on any of data obtained by applying the compensation processing to data represented in the second representation format, while performing, when an operation to be processed is an addition or a subtraction, the operation processing on data represented in a two's complement representation. ### Claim 14 (depends on 11) The signal processing method according to claim 11, comprising: performing a fast Fourier transform or an inverse fast Fourier transform using both a two's complement representation and the second representation format as data representation formats, wherein the operation processing includes: butterfly operation processing performing butterfly operation processing; and twiddle factor multiplication processing performing twiddle factor multiplication processing, wherein the storage processing includes data reordering processing rearranging an order of a plurality of data, wherein the butterfly operation processing performs the butterfly operation processing on data represented in the two's complement representation, wherein the twiddle factor multiplication processing performs operation processing on data obtained by applying compensation processing to data represented in the second representation format, for multiplication processing, and performs operation processing on data represented in a two's complement representation, for addition processing, and wherein the data reordering processing performs storage processing on data represented in the second representation format. ### Claim 15 (canceled) ### Claim 16 A non-transitory computer-readable storage medium storing thereon a program causing a computer to execute: a storage processing on data represented in a second representation format, wherein when a value of the data is positive or zero the second representation format is identical to a representation format of two's complement, while, when the value of the data is negative, the second representation format is a representation format in which all bits other than a most significant bit indicating a sign in a two's complement representation of the data are inverted; and an operation processing on at least any one of data represented in the two's complement representation or data obtained by applying compensation processing to data represented in the second representation format. ### Claim 17 (depends on 11) The signal processing method according to claim 11, comprising: in the operation processing, performing a sign operation on one or more sign bits of one or more individual items of data of operation target in the second representation format with the compensation processing applied thereto to output an operation result as a sign bit; and performing an unsigned operation on one or more magnitude parts other than the one or more sign bits of the one or more individual items of data of operation target represented in the second representation format with the compensation processing applied thereto to output a format with the compensation processing applied thereto to output a result of the operation as a magnitude part. ### Claim 18 (depends on 16) The non-transitory computer-readable storage medium according to claim 16, storing thereon the program causing a computer to execute processing comprising: in the compensation processing, adding a value one to M bits from a least significant bit (where M is a positive integer and not more than N) in data of N bits (where N is a predetermined positive integer) when the data of N bits (N being a positive integer) represented in the second representation format has a negative value. ### Claim 19 (depends on 16) The non-transitory computer-readable storage medium according to claim 16, storing thereon the program causing a computer to execute processing comprising in the operation processing, performing, when an operation to be processed is a multiplication or a division, the operation processing on any of data obtained by applying the compensation processing to data represented in the second representation format, while performing, when an operation to be processed is an addition or a subtraction, the operation processing on data represented in a two's complement representation. ### Claim 20 (depends on 16) The non-transitory computer-readable storage medium according to claim 16, storing thereon the program causing a computer to execute processing comprising: in the operation processing, performing a sign operation on one or more sign bits of one or more individual items of data of operation target in the second representation format with the compensation processing applied thereto to output an operation result as a sign bit; and performing an unsigned operation on one or more magnitude parts other than the one or more sign bits of the one or more individual items of data of operation target represented in the second representation format with the compensation processing applied thereto to output a result of the operation as a magnitude part. ### Claim 21 (depends on 16) The non-transitory computer-readable storage medium according to claim 16, storing thereon the program causing a computer to execute processing comprising: performing a fast Fourier transform or an inverse fast Fourier transform using both a two's complement representation and the second representation format as data representation formats, wherein the operation processing includes: butterfly operation processing performing butterfly operation processing; and twiddle factor multiplication processing performing twiddle factor multiplication processing, wherein the operation processing includes: data reordering processing rearranging an order of a plurality of data, wherein the butterfly operation processing performs the butterfly operation processing on data represented in the two's complement representation, wherein the twiddle factor multiplication processing performs operation processing on data obtained by applying compensation processing to data represented in the second representation format, for multiplication processing, and performs operation processing on data represented in a two's complement representation, for addition processing, and wherein the data reordering processing performs storage processing on data represented in the second representation format.