# US 2021/0334231 A1 · System to enable display detect and method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0334231 A1 - Document ID: US20210334231A1 - Status: Published application - Kind: A1 - Application number: 16/861,021 - Filed: 2020-04-28 - Published: 2021-10-28 - Earliest claimed: 2020-04-28 - Assignees: Dell Products L.P. - Applicants: Dell Products, LP - Inventors: Eric Sendelbach - Web page: https://patentgrep.com/patent/US20210334231A1 ## CPC - G06F 13/4081: {Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004)} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract A method may include executing basic input/output system (BIOS) instructions to initialize an information handling system. The initialization may include generating a hot-plug detect (HPD) override request. The method may further include receiving the HPD override request at a general purpose input/output (GPIO) device. In response to receiving the HPD override request, the GPIO may assert an active-low signal at an interconnect electrically connected to a HPD terminal of a graphics display receptacle, the receptacle for coupling a graphics processing unit to a graphics display device. ## Claims ### Claim 1 An information handling system comprising: a display receptacle to couple the information handling system to a graphics display device, the receptacle including a hot-plug detect (HPD) terminal configured to receive an HPD signal from the graphics display device; a general purpose input/output (GPIO) device, an output of the GPIO device electrically coupled to the HPD terminal; and a central processing unit (CPU) to execute basic input/output system (BIOS) instructions, the BIOS instructions to configure the GPIO to assert an active-low signal at an interconnect electrically connected to the HPD terminal. ### Claim 2 (depends on 1) The information handling system of claim 1, further comprising an embedded controller (EC), and wherein the GPIO is included at the EC. ### Claim 3 (depends on 1) The information handling system of claim 1, further comprising a chipset functionally coupled to the CPU, and wherein the GPIO is included at the chipset. ### Claim 4 (depends on 1) The information handling system of claim 1, further comprising an integrated graphics processing unit (GPU), the integrated GPU coupled to the display receptacle. ### Claim 5 (depends on 1) The information handling system of claim 1, further comprising a BIOS configuration setup interface, the interface including an option to enable and disable configuring the GPIO to assert the active-low signal. ### Claim 6 (depends on 1) The information handling system of claim 1, wherein the display receptacle is a Display Port receptacle. ### Claim 7 (depends on 1) The information handling system of claim 1, wherein the display receptacle is a High-Definition Multimedia Interface receptacle. ### Claim 8 (depends on 1) The information handling system of claim 1, wherein the GPIO is configured to discontinue the assertion of the active-low signal prior to handing control of the information handling system to an operating system. ### Claim 9 (depends on 1) The information handling system of claim 1, wherein the GPIO is configured to discontinue the assertion of the active-low signal after the BIOS transfers control of the information handling system to an operating system. ### Claim 10 A method comprising: executing basic input/output system (BIOS) instructions to initialize an information handling system, the initialization including generating a hot-plug detect (HPD) override request; receiving the HPD override request at a general purpose input/output (GPIO) device; and in response to receiving the HPD override request, asserting an active-low signal at an interconnect electrically connected to an HPD terminal of a graphics display receptacle, the receptacle for coupling a graphics processing unit to a graphics display device. ### Claim 11 (depends on 10) The method of claim 10, wherein the GPIO is included at an embedded controller. ### Claim 12 (depends on 10) The method of claim 10, wherein the GPIO is included at a chipset. ### Claim 13 (depends on 10) The method of claim 10, wherein the display receptacle is coupled to an integrated graphics processing unit included at the information handling system. ### Claim 14 (depends on 10) The method of claim 10, wherein the information handling system provides a BIOS configuration setup interface, the interface including an option to enable and disable configuring the GPIO to assert the active-low signal. ### Claim 15 (depends on 10) The method of claim 10, wherein the GPIO is configured to discontinue the assertion of the active-low signal prior to handing control of the information handling system to an operating system. ### Claim 16 (depends on 10) The method of claim 10, wherein the GPIO is configured to discontinue the assertion of the active-low signal after the BIOS transfers control of the information handling system to an operating system. ### Claim 17 A circuit board comprising: a graphics processing unit (GPU); a display receptacle to couple the GPU to a graphics display device, the receptacle including a hot-plug detect (HPD) terminal configured to receive an HPD signal from the graphics display device; a general purpose input/output (GPIO) device, an output of the GPIO device electrically coupled to the HPD terminal; and a central processing unit to execute basic input/output system (BIOS) instructions, the BIOS instructions to configure the GPIO to assert an active-low signal at an interconnect electrically connected to the HPD terminal. ### Claim 18 (depends on 17) The circuit board of claim 17, further comprising an embedded controller (EC), wherein the GPIO is included at the EC. ### Claim 19 (depends on 17) The circuit board of claim 17, further comprising a chipset functionally coupled to a central processing unit, wherein the GPIO is included at the chipset. ### Claim 20 (depends on 17) The circuit board of claim 17, wherein the GPU is an integrated GPU permanently installed at the circuit board.