# US 2021/0334162 A1 · Fpga acceleration system for msr codes

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- Number: US 2021/0334162 A1
- Document ID: US20210334162A1
- Status: Published application
- Kind: A1
- Application number: 17/367,315
- Filed: 2021-07-02
- Published: 2021-10-28
- Earliest claimed: 2018-12-14
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Mian QIN; Joo Hwan LEE; Rekha PITCHUMANI; Yang Seok KI
- Web page: https://patentgrep.com/patent/US20210334162A1

## CPC

- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

## Claims

### Claim 1

An apparatus comprising:
a host interface circuit configured to receive an offloading instruction from a host processing device configured to manage a storage system, wherein the offloading instruction instructs the apparatus to compute an error correction code associated with data elements stored by the storage system;
a memory interface circuit configured to receive the data elements from the storage system; and
an error code computation circuit configured to compute at least a portion of the error correction code.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the storage system comprises a distributed storage system.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the memory interface circuit is configured to automatically write an output of the error code computation circuit to an external memory.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the data elements are associated with a number of data nodes of the storage system, wherein a data node stores a portion of the data elements at a remote location; and
wherein the error code computation circuit is reconfigurable based upon the number of data nodes.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the error code computation circuit comprises:
a tree of alternating multiplication circuits and additional circuits.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the multiplication circuits comprise lookup tables; and
wherein the additional circuits comprise XOR gates.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the error code computation circuit is reprogrammable by the host processing device.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the error correction code comprises a Minimum Storage Regenerating (MSR) code.

### Claim 9

A system comprising:
a memory configured to store data elements stored by a storage system;
a host processing device configured to configured to manage the storage system and offload a computation of an error correction code to a reprogrammable processing device; and
the reprogrammable processing device configured to compute the error correction code, wherein the reprogrammable processing device comprises:
a reconfigurable pipeline that computes at least a portion of the error correction code and is reconfigured based upon a number of data elements.