# US 2021/0334152 A1 · Semiconductor device and system using the same

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- Number: US 2021/0334152 A1
- Document ID: US20210334152A1
- Status: Published application
- Kind: A1
- Application number: 16/859,463
- Filed: 2020-04-27
- Published: 2021-10-28
- Earliest claimed: 2020-04-27
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Kiyoshi HAYASE; Shinichi SHIBAHARA; Yuki HAYAKAWA; Yoichi YUYAMA
- Web page: https://patentgrep.com/patent/US20210334152A1

## CPC

- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G06F 11/1604: {where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware}
- G06F 11/0721: {within a central processing unit [CPU]}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor device has a timer unit and a processing unit. The timer unit includes a binary counter, a first converter that converts a first count value output from the binary counter to a gray code to output as first gray code data. The processing unit includes a first synchronizer that captures the first gray code data transferred from the timer unit in synchronization with the system clock signal and outputs the captured first gray code data as second gray code data, and a fault detection unit that generates a data for fault detection based on the first gray code data transferred from the timer unit and compares a second count value based on the second gray code data with a third counter value based on the data for fault detection.

## Claims

### Claim 1

A semiconductor device comprising:
a timer unit having:
a binary counter; and
a first converter configured to convert a first count value output from the binary counter to a gray code to output as a first gray code data; and
a processing unit having:
a first synchronizer configured to capture the first gray code data transferred from the timer unit in synchronization with a system clock signal to output as a second gray code data; and
a fault detection unit configured to generate data for fault detection based on the first gray code data transferred from the timer unit, ii) compare a second count value based on the second gray code data with a third count value based on the data for fault detection, and iii) output a fault detection signal indicating whether a fault is detected based on a comparison result.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the fault detection unit determines whether a difference between the second count value and the third count value is equal to or smaller than a predetermined value.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the fault detection unit outputs the fault detection signal when the difference is larger than the predetermined value.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the fault detection unit determines whether an absolute value of a difference between the second count value and the third count value is equal to or smaller than a predetermined value, and outputs an fault detection signal when the absolute value of the difference is larger than the predetermined value.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the fault detection unit determines whether a difference between the second count value and the third count value is in a predetermined value range.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the fault detection unit outputs a fault detection signal when the difference is outside the predetermined value range.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein the first synchronizer receives the first gray code data through a first path, and
wherein the fault detection unit further includes a second synchronizer capturing the first gray code data transferred through a second path different from the first path in synchronization with the system clock signal to output as the data for fault detection.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1,
wherein the processing unit further comprises a second converter converts the second gray code data to a second binary code data, and
wherein the fault detection unit comprises:
a third converter converting the data for fault detection to a third binary code data; and
a comparator a count value based on the second binary code data with a count value based on the third binary code data.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1,
wherein the processing unit further includes:
a second converter is coupled to the first synchronizer and converts the second gray code data to a second binary code data; and
a buffer is coupled to the second converter, captures the second binary code data and outputs the captured second binary code data in response to a next system clock signal as a third binary code data,
wherein the second count value is a value based on the third binary code data, and
wherein the third count value is a value based on the second binary code data.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a processing execution unit receiving the second count value.

### Claim 11

A semiconductor system comprising:
a timer unit having a binary counter and a first converter, the first converter converting a first count value output from the binary counter to a gray code to output as a first gray code data; and
a plurality of processing units receiving the first gray code data from the timer unit,
wherein each of the plurality of processing units includes:
a first synchronizer capturing the first gray code data transferred from the timer unit in synchronization with a system clock signal to output a second gray code data; and
a fault detection unit generating a data for fault detection based on the first gray code data transferred from the timer unit, comparing a second count value based on the second gray code data with a third count value based on the data for fault detection, and outputting a fault detection signal indicating whether a fault is detected based on a comparison result.

### Claim 12 (depends on 11)

The semiconductor system according to claim 11 further comprising:
a fault management unit to which the fault detection signal of each fault detection unit of the plurality of processing units is notified.

### Claim 13 (depends on 11)

The semiconductor system according to claim 11, wherein the plurality of processing units are mutually asynchronously operated.

### Claim 14 (depends on 11)

The semiconductor system according to claim 11, wherein each of the plurality of processing units includes a plurality of processing execution units to which the second count value is commonly supplied.

### Claim 15 (depends on 1)

The semiconductor device according to claim 1, wherein the timer unit and the processing unit are mutually asynchronously operated.