# US 2021/0334138 A1 · Technologies for pre-configuring accelerators by predicting bit-streams

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- Number: US 2021/0334138 A1
- Document ID: US20210334138A1
- Status: Published application
- Kind: A1
- Application number: 17/365,898
- Filed: 2021-07-01
- Published: 2021-10-28
- Earliest claimed: 2017-08-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Francesc GUIM BERNAT; Susanne M. BALLE; Slawomir PUTYRSKI; Rahul KHANNA; Paul DORMITZER
- Web page: https://patentgrep.com/patent/US20210334138A1

## CPC

- G06F 9/4887: {involving deadlines, e.g. rate based, periodic}
- G06F 9/48: Program initiating; Program switching, e.g. by interrupt
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU]
- G06F 9/5005: {to service a request}
- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 9/5044: {considering hardware capabilities}
- G06F 9/505: {considering the load}
- G06F 9/5055: {considering software capabilities, i.e. software resources associated or available to the machine}
- G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)}
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06N 5/02: Knowledge representation; Symbolic representation
- G06F 2117/08: HW-SW co-design, e.g. HW-SW partitioning
- G06F 2209/5019: Workload prediction
- G06F 2209/508: Monitor
- G06F 2209/509: Offload
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.

## Claims

### Claim 1

A system comprising:
a plurality of Field Programmable Gate Array (FPGA) resources;
a plurality of compute devices; and
an orchestrator in communication with the plurality of compute devices and the plurality of FPGA resources, the orchestrator to manage an FPGA bit-stream library, the orchestrator to register a bit-stream in the FPGA bit-stream library to one of the plurality of FPGA resources.

### Claim 2 (depends on 1)

The system of claim 1, wherein the FPGA bit-stream library to store bit-streams that are registered on the FPGA resources.

### Claim 3 (depends on 1)

The system of claim 1, wherein the orchestrator to track bit-streams registered on the FPGA resources.

### Claim 4 (depends on 1)

The system of claim 1, wherein a compute device to offload tasks to the FPGA resources.

### Claim 5 (depends on 1)

The system of claim 1, wherein the orchestrator to support a cloud operating environment.

### Claim 6 (depends on 1)

The system of claim 1, wherein a FPGA resource includes a plurality of kernels.

### Claim 7 (depends on 1)

The system of claim 1, wherein a FPGA resource to fetch the bit-stream from the FPGA bit-stream library.

### Claim 8

A method comprising:
managing, by an orchestrator, a Field Programmable Gate Array (FPGA) bit-stream library, the orchestrator in communication with a plurality of compute devices and a plurality of FPGA resources; and
registering, by the orchestrator, a bit-stream in the FPGA bit-stream library to one of the plurality of FPGA resources.

### Claim 9 (depends on 8)

The method of claim 8, wherein the bit-stream library to store bit-streams that are registered on the FPGA resources.

### Claim 10 (depends on 8)

The method of claim 8, wherein the orchestrator to track the FPGA bit-streams registered on the FPGA resources.

### Claim 11 (depends on 8)

The method of claim 8, wherein q compute device to offload tasks to the FPGA resources.

### Claim 12 (depends on 8)

The method of claim 8, wherein the orchestrator to support a cloud operating environment.

### Claim 13 (depends on 8)

The method of claim 8, wherein a FPGA resource includes a plurality of kernels.

### Claim 14 (depends on 8)

The method of claim 8, wherein a FPGA resource to fetch the bit-stream from the FPGA bit-stream library.

### Claim 15

One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, when executed by a compute device cause the compute device to:
manage a Field Programmable Gate Array (FPGA) bit-stream library; and
register a bit-stream in the FPGA bit-stream library to one of a plurality of FPGA resources.

### Claim 16 (depends on 15)

The one or more non-transitory machine-readable storage media of claim 15, wherein the bit-stream library to store bit-streams that are registered on the plurality of FPGA resources.

### Claim 17 (depends on 15)

The one or more non-transitory machine-readable storage media of claim 15, wherein the plurality of instructions, when executed, further cause a compute device to track the FPGA bit-streams registered on the FPGA resources.

### Claim 18 (depends on 15)

The one or more non-transitory machine-readable storage media of claim 15, wherein the plurality of instructions, when executed, further cause a compute device to offload tasks to the FPGA resources.

### Claim 19 (depends on 15)

The one or more non-transitory machine-readable storage media of claim 15, wherein the plurality of instructions, when executed, further cause a compute device to support a cloud operating environment.

### Claim 20 (depends on 15)

The one or more non-transitory machine-readable storage media of claim 15, wherein a FPGA resource includes a plurality of kernels.