# US 2021/0334104 A1 · Method and apparatus for renaming source operands of instructions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0334104 A1 - Document ID: US20210334104A1 - Status: Published application - Kind: A1 - Application number: 17/370,098 - Filed: 2021-07-08 - Published: 2021-10-28 - Earliest claimed: 2019-06-04 - Inventors: Dejan Spasov - Web page: https://patentgrep.com/patent/US20210334104A1 ## CPC - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/384: {Register renaming} - G06F 9/30101: {Special purpose registers} - G06F 9/3802: {Instruction prefetching} - G06F 9/3863: {using multiple copies of the architectural state, e.g. shadow registers} - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A renaming unit configured to rename source operands of instructions in a group. A renaming register maintains architectural to physical register mappings. Architectural to physical register mappings propagate from the renaming register through a chain of update units (U) over bus lines denoted with the architectural registers 0 to L. Update units (U) sequentially, in program order, insert physical register identifiers PR(i) allocated to instructions I(i) with destination operands DOP(i) on bus lines denoted with the destination operands DOP(i). Source operands of an instruction I(i) may be renamed to physical register identifiers after physical register identifiers allocated to instructions older than I(i) are sequentially, in program order, inserted on the bus lines, but before physical register identifiers allocated to I(i) and younger instructions are inserted on the bus lines. A source operand SOP(i) is renamed to a physical register identifier that propagates on a bus line denoted with SOP(i). ## Claims ### Claim 1 A processor comprising: a fetch and decode unit configured to output a group of one or more instructions; a free list configured to output a first physical register identifier of a first physical register allocated to a first instruction with a first destination operand from the group; a renaming register comprising a plurality of fields, wherein a second physical register identifier from architectural to physical register mappings is stored in a first field, wherein the second physical register identifier identifies a second physical register allocated to youngest instruction from prior group of instructions with destination operand equal to a first architectural register. ### Claim 2 (depends on 1) The processor in claim 1 comprising: one or more circuits, wherein a first circuit from the one or more circuits comprises a first decoder and a first plurality of 2-to-1 multiplexers, wherein a first 2-to-1 multiplexer from the first plurality of 2-to-1 multiplexers is coupled to receive the first physical register identifier, wherein the first decoder is coupled to receive the first destination operand, wherein a first output signal line from the first decoder is coupled as selection control to the first 2-to-1 multiplexer, wherein the first output signal line is asserted if the first destination operand is equal to the first architectural register, wherein the first 2-to-1 multiplexer outputs the first physical register identifier if the first signal line is asserted. ### Claim 3 (depends on 2) The processor in claim 2, wherein one 2-to-1 multiplexer from each circuit of said one or more circuits is coupled in a chain, wherein a second 2-to-1 multiplexer from the chain is coupled to receive the second physical register identifier, wherein the first 2-to-1 multiplexer is coupled in the chain to receive a third physical register identifier, wherein the first 2-to-1 multiplexer is configured to output the third physical register identifier if the first signal line is not asserted. ### Claim 4 (depends on 2) The processor in claim 2, wherein the first 2-to-1 multiplexer is coupled to receive the second physical register identifier, wherein the first 2-to-1 multiplexer is configured to output the second physical register identifier if the first signal line is not asserted. ### Claim 5 (depends on 3) The processor in claim 3, wherein the first field is coupled to store physical register identifier outputted from a last 2-to-1 multiplexer in the chain. ### Claim 6 (depends on 3) The processor in claim 3 comprising: a plurality of read multiplexers, wherein a first read multiplexer from the plurality of read multiplexers is coupled to receive a first source operand of the first instruction as selection control, wherein the first read multiplexer is coupled to receive the third physical register identifier, wherein the first read multiplexer is configured to output the third physical register identifier if the first source operand is equal to the first architectural register. ### Claim 7 (depends on 1) The processor in claim 1, wherein said one or more instructions in the group are from one or more threads, the processor comprising: one or more circuits, wherein a first circuit from the one or more circuits comprises a first decoder and a first plurality of 2-to-1 multiplexers, wherein a first 2-to-1 multiplexer from the first plurality of 2-to-1 multiplexers is coupled to receive the first physical register identifier, wherein the first decoder is coupled to receive the first destination operand, wherein a first output signal line from the first decoder is coupled as selection control to the first 2-to-1 multiplexer, wherein the first output signal line is asserted if the first destination operand is equal to the first architectural register and the first instruction belongs to a first thread, wherein the first 2-to-1 multiplexer outputs the first physical register identifier if the first signal line is asserted. ### Claim 8 (depends on 7) The processor in claim 7, wherein one 2-to-1 multiplexer from each circuit of the one or more circuits is coupled in a chain, wherein a second 2-to-1 multiplexer from the chain is coupled to receive the second physical register identifier, wherein the first 2-to-1 multiplexer is coupled in the chain to receive a third physical register identifier, wherein the first 2-to-1 multiplexer is configured to output the third physical register identifier if the first signal line is not asserted. ### Claim 9 (depends on 8) The processor in claim 8, wherein the first field is coupled to store physical register identifier outputted from a last 2-to-1 multiplexer in the chain. ### Claim 10 (depends on 8) The processor in claim 8 comprising: a plurality of read multiplexers, wherein a first read multiplexer from the plurality of read multiplexers is coupled to receive a first source operand of the first instruction as selection control, wherein the first read multiplexer is coupled to receive the third physical register identifier, wherein the first read multiplexer is configured to output the third physical register identifier if the first source operand is equal to the first architectural register. ### Claim 11 A processor comprising: a fetch and decode unit configured to output a group of one or more instructions; a free list configured to output a first physical register identifier of a first physical register allocated to a first instruction with a first destination operand from the group; one or more circuits, wherein a first circuit from the one or more circuits comprises a first decoder and a first plurality of 2-to-1 multiplexers, wherein a first 2-to-1 multiplexer from the first plurality of 2-to-1 multiplexers is coupled to receive the first physical register identifier, wherein the first decoder is coupled to receive the first destination operand, wherein a first output signal line from the first decoder is coupled as selection control to the first 2-to-1 multiplexer, wherein the first output signal line is asserted if the first destination operand is equal to a first architectural register, wherein the first 2-to-1 multiplexer outputs the first physical register identifier if the first signal line is asserted. ### Claim 12 (depends on 11) The processor in claim 11 comprising: a renaming register comprising a plurality of fields, wherein a second physical register identifier from architectural to physical register mappings is stored in a first field, wherein the second physical register identifier identifies a second physical register allocated to youngest instruction from prior group of instructions with destination operand equal to the first architectural register. ### Claim 13 (depends on 12) The processor in claim 12, wherein one 2-to-1 multiplexer from each circuit of said one or more circuits is coupled in a chain, wherein a second 2-to-1 multiplexer from the chain is coupled to receive the second physical register identifier, wherein the first 2-to-1 multiplexer is coupled in the chain to receive a third physical register identifier, wherein the first 2-to-1 multiplexer is configured to output the third physical register identifier if the first signal line is not asserted. ### Claim 14 (depends on 13) The processor in claim 13, wherein the first field is coupled to store physical register identifier outputted from a last 2-to-1 multiplexer in the chain. ### Claim 15 (depends on 13) The processor in claim 13, wherein said one or more instructions are from one or more threads, wherein the first decoder is configured to assert the first signal line only if the first instruction belongs to a first thread. ### Claim 16 (depends on 13) The processor in claim 13 comprising: a plurality of read multiplexers, wherein a first read multiplexer from the plurality of read multiplexers is coupled to receive a first source operand of the first instruction as selection control, wherein the first read multiplexer is coupled to receive the third physical register identifier, wherein the first read multiplexer is configured to output the third physical register identifier if the first source operand is equal to the first architectural register. ### Claim 17 A method for renaming source operands of instructions comprising: receiving a group of instructions I(1), I(2), . . . , I(n); allocating physical registers to instructions with destination operand; maintaining a renaming register with a plurality of fields, wherein a first physical register identifier from architectural to physical register mappings is stored in a first field, wherein the first physical register identifier identifies a first physical register allocated to youngest instruction from prior group of instructions with destination operand equal to a first architectural register. ### Claim 18 (depends on 17) The method in claim 17 comprising: inserting the first physical register identifier on a first bus line. ### Claim 19 (depends on 18) The method in claim 18, wherein for each instruction I(i) in the group, where i=1, 2, . . . , n, the method comprising: renaming source operands of instruction I(i), wherein a first source operand of instruction I(i) is renamed to a second physical register identifier that propagates on a second bus line, wherein the second physical register identifier is allocated to youngest instruction, older than I(i), with destination operand equal to the first source operand; if instruction I(i) comprises destination operand: inserting a third physical register identifier that identifies a third physical register allocated to I(i) on a third bus line. ### Claim 20 (depends on 19) The method in claim 19 comprising: storing physical register identifiers in the renaming register, wherein the third physical register identifier is stored in the first field if I(i) is youngest instruction with destination operand equal to the first architectural register.