# US 2021/0334101 A1 · Frequency scaling for per-core accelerator assignments > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0334101 A1 - Document ID: US20210334101A1 - Status: Published application - Kind: A1 - Application number: 16/933,369 - Filed: 2020-07-20 - Published: 2021-10-28 - Earliest claimed: 2020-04-24 - Assignees: Intel Corporation - Inventors: Stephen T. Palermo; Srihari Makineni; Shubha Bommalingaiahnapallya; Neelam Chandwani; Rany T. Elsayed; Udayan Mukherjee; Lokpraveen Mosur; Adwait Purandare - Web page: https://patentgrep.com/patent/US20210334101A1 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3879: {for non-native instruction execution, e.g. executing a command; for Java instruction set} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/30189: {according to execution mode, e.g. mode flag} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads. ## Claims ### Claim 1 A processor, comprising: a plurality of cores, wherein at least a portion of the plurality cores can be selectively configured and comprise, a first block of circuitry configured to implement an instruction set architecture (ISA) supporting a first set of instructions; and one or more ISA extension units comprising circuitry separate from the first block of circuitry configured to implement a second set of instructions comprising one or more extended instructions that are not included in the first set of instructions, wherein the ISA extension unit can be selectively enabled or disabled. ### Claim 2 (depends on 1) The processor of claim 1, wherein each of the plurality of cores includes the first block of circuitry configured to implement the ISA supporting the first set of instructions. ### Claim 3 (depends on 1) The processor of claim 1, wherein each of the plurality of cores can be selectively configured on a per-core basis. ### Claim 4 (depends on 1) The processor of claim 1, wherein the plurality of cores include power frequency control logic that enables the frequency of the cores to be dynamically adjusted on a per-core basis. ### Claim 5 (depends on 1) The processor of claim 1, wherein the one or more instructions in the second set of instructions comprise at least one Advanced Vector Extensions (AVX) instruction. ### Claim 6 (depends on 5) The processor of claim 5, wherein the at least one AVX instruction comprises an AVX3-512 5G instruction. ### Claim 7 (depends on 1) The processor of claim 1, wherein the one or more instructions in the second set of instructions comprise at least one Advanced Matrix Extensions (AMX) instruction. ### Claim 8 (depends on 1) The processor of claim 1, wherein a first set of cores among the plurality of cores have a configuration without an ISA extension unit, and a second set of cores among the plurality of cores comprise cores with an ISA extension unit that can be selectively enable or disabled. ### Claim 9 (depends on 1) The processor of claim 1, wherein the first set of instructions include at least one Streaming SIMD Extensions (SSE) instruction and one or more Advanced Vector Extensions (AVX) instructions. ### Claim 10 (depends on 1) The processor of claim 1, wherein the plurality of cores includes cores that are autonomously configured. ### Claim 11 (depends on 10) The processor of claim 10, wherein an autonomously configured core is configured to: execute an instruction thread using the first block of circuitry while the one or more ISA extension units are disabled; detect an instruction in the instruction thread that is among the second set of instructions, and in response, enable at least one ISA extension unit; and execute the instruction on an enabled ISA extension unit. ### Claim 12 A method implemented on a processor including a plurality of cores, at least a portion of which are configurable cores including one or more instruction set architecture (ISA) extension units supporting one or more extended instructions, comprising: configuring a first set of configurable cores to have at least one ISA extension unit enabled; and employing configurable cores among the first set of configurable cores to execute one or more extended instructions. ### Claim 13 (depends on 12) The method of claim 12, further comprising: operating a second set of cores from among the plurality cores at a first frequency; and operating the first set of configurable cores at a second frequency. ### Claim 14 (depends on 13) The method of claim 13, wherein the first frequency is higher than the second frequency, and the first and second frequencies are selected such that the processor is operated within thermal design power specifications. ### Claim 14 (depends on 13) The method of claim 13, wherein the first and second frequencies are selected such that the processor is operated at a maximum turbo mode. ### Claim 16 (depends on 12) The method of claim 12, wherein the one or more extended instructions comprises an AVX3-512 5G instruction. ### Claim 17 (depends on 12) The method of claim 12, further comprising, executing software comprising compiled instructions including AVX3-512 5G instructions on one or more configurable cores having an enabled ISA extension unit to perform virtual Radio Access Network (vRAN) 5G Layer 1 signal processing. ### Claim 18 (depends on 12) The method of claim 12, further comprising: executing an instruction thread on a core while the one or more ISA extension units for the core are disabled; detecting an extended instruction in the instruction thread, and in response, enabling at least one ISA extension unit for the core; and executing the instruction on an enabled ISA extension unit for the core. ### Claim 19 A server platform comprising: a processor, having a plurality of cores, wherein each of the plurality of cores includes a first block of circuitry configured to implement an instruction set architecture (ISA) supporting a first set of instructions, and wherein at least a portion of the plurality cores include one or more selectively enablable ISA extension units comprising circuitry separate from the first block of circuitry configured to implement a second set of instructions comprising one or more extended instructions that are not included in the first set of instructions, the processor further including at least one memory controller and at least one input-output (TO) interface; first memory, operatively coupled to a first memory controller; and a Network Interface Controller (NIC) operatively coupled to an IO interface. ### Claim 20 (depends on 19) The server platform of claim 19, wherein the processor includes a first set of cores including the selectively enablable ISA extension unit and a second set of cores that do not include the selectively enablable ISA extension unit. ### Claim 21 (depends on 19) The server platform of claim 19, wherein each of the processor cores includes power frequency control logic that enables the frequency of the core to be dynamically adjusted on a per-core basis. ### Claim 22 (depends on 20) The server platform of claim 20, wherein the server platform is configured to: operate the first set of cores at a first frequency; and operate the second set of cores at a second frequency. ### Claim 23 (depends on 19) The server platform of claim 19, wherein the second set of instructions include a AVX3-512 5G instruction. ### Claim 24 (depends on 23) The server platform of claim 23, further comprising: software comprising compiled instructions including AVX3-512 5G instructions, loaded into the first memory, wherein the software is configured to be executed on one or more cores having an enabled ISA extension unit to perform virtual Radio Access Network (vRAN) 5G Layer 1 signal processing. ### Claim 25 (depends on 19) The server platform of claim 19, wherein the plurality of cores includes cores that are autonomously configured.