# US 2021/0334033 A1 · Memory device and method reading data

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- Number: US 2021/0334033 A1
- Document ID: US20210334033A1
- Status: Published application
- Kind: A1
- Application number: 17/090,726
- Filed: 2020-11-05
- Published: 2021-10-28
- Earliest claimed: 2020-04-27
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: SUNGHYE CHO; KIJUN LEE; SUNG-RAE KIM; CHANKI KIM; YEONGGEOL SONG; YESIN RYU; JAEYOUN YOUN; MYUNGKYU LEE
- Web page: https://patentgrep.com/patent/US20210334033A1

## CPC

- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0673: {Single storage device}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

## Claims

### Claim 1

A memory device comprising:
a memory chip including memory cells; and
a logic chip configured to control the memory chip,
wherein the logic chip reads a codeword including N data units from the memory chip, and perform error correction decoding on the codeword to correct errors in M data units of the N data units, such that when the M data units correspond to a common component of the memory chip, the logic chip is configured to correct the errors of the M data units, and when the M data units do not correspond to the common component of the memory chip, the logic chip is configured to process the errors of the M data units as an uncorrectable error,
N is a positive integer, and
M is a positive integer less than N.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory chip includes:
a sub-word line connected to the memory cells;
a sub-word line driver configured to drive the sub-word line;
a word line connected to the sub-word line driver; and
a row decoder connected with the word line, and
the common component is the sub-word line driver.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the memory chip includes:
a sub-word line connected to the memory cells;
a sub-word line driver configured to drive the sub-word line;
a word line connected to the sub-word line driver; and
a row decoder connected with the word line, and
the common component is the sub-word line.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein, processing of the uncorrectable error includes outputting a signal to an external host device indicating that the uncorrectable error has occurred.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the logic chip is configured to communicate with the external host device through data lines and control signal lines, and
the logic chip outputs the signal to the external host device through at least one of the data lines.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein the logic chip is configured to communicate with the external host device through data lines and control signal lines, and
the logic chip outputs the signal to the external host device through at least one of the control signal lines.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein each of the N data units includes an 8-bit symbol.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein N=36.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein M=2.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the logic chip is configured to manage the uncorrectable error based on at least one option defined by an external host device.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein the at least one option includes a setting associated with whether to process the errors of the M data units as the uncorrectable error, or whether to correct the errors of the M data units when the M data units do not correspond to the common component of the memory chip.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein the at least one option includes a setting associated with whether to output to the external host device information indicating that the uncorrectable error occurs or information indicating that the uncorrectable error occurs due to no correspondence to the common component and the M data units do not correspond to the common component of the memory chip.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein the at least one option includes a setting associated with whether the logic chip stores addresses of the M data units.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the at least one option further includes a setting associated with whether the logic chip refuses an access to the addresses of the M data units.

### Claim 15

A memory device comprising:
a memory chip including memory cells; and
a logic chip configured to control the memory chip,
wherein the logic chip is configured to read a codeword including N data units from the memory chip, and perform error correction decoding on the codeword to correct errors in M data units of the N data units, such that when the M data units do not correspond to a data corruption pattern, the logic chip is configured to correct the errors of the M data units, and when the M data units correspond to the data corruption pattern, the logic chip is configured to process the errors of the M data units as an uncorrectable error,
N is a positive integer, and
M is a positive integer less than N.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the data corruption pattern is based on locations of memory cells in which the memory chip writes the M data units.

### Claim 17 (depends on 15)

The memory device of claim 15, wherein the logic chip includes:
a first error correction device configured to perform a first error correction decoding a portion of the codeword to generate a first sub-codeword; and
a second error correction device configured to perform a second error correction decoding a remaining portion of the codeword to generate a second sub-codeword.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the error in the M data units include a first error and a second error, and
the data corruption pattern includes a pattern in which a location of the first error in the first sub-codeword is independent of a location of the second error in the second sub-codeword.

### Claim 19

A method for reading data from a memory device including memory cells, the method comprising:
reading a codeword from the memory cells;
correcting errors when a number of the errors in the codeword is less than a maximum number of correctable errors;
correcting errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line; and
outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
receiving a second codeword;
performing a first error correction decoding on a portion of the second codeword to generate a first sub-codeword;
performing a second error correction decoding on a remaining portion of the second codeword to generate a second sub-codeword; and
writing the first sub-codeword and the second sub-codeword in the memory cells as the codeword by writing a first data unit of the first sub-codeword in first memory cells connected with a first sub-word line from among the memory cells, and writing a second data unit of the second sub-codeword in second memory cells connected with the first sub-word line from among the memory cells.