# US 2021/0333327 A1 · Controller for a memory component > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0333327 A1 - Document ID: US20210333327A1 - Status: Published application - Kind: A1 - Application number: 16/624,948 - Filed: 2019-05-31 - Published: 2021-10-28 - Earliest claimed: 2019-05-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Antonino Mondello; Alberto Troia - Web page: https://patentgrep.com/patent/US20210333327A1 ## CPC - G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines - G01R 31/318555: {Control logic} - G01R 31/318558: {Addressing or selecting of subparts of the device under test} - G01R 31/318597: {JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32)} - G06F 9/328: {for runtime instruction patching} - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F 9/44521: {Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading} - G06F 11/0736: {in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function (testing or monitoring of automated control systems G05B23/02)} - G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A controller for a memory component comprises a processing unit and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; the processing unit is configured to capture a memory address of a program instruction to be executed, compare the memory address with a reference value, and, based on that comparison, enable/restricting actions associated with the program instruction. A related memory component and related methods are also disclosed. ## Claims ### Claim at position 1 1-27. (canceled) ### Claim 28 A controller for a memory component, comprising: a processing unit; and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; wherein the processing unit is configured to: receive a memory address of a program instruction to be executed; compare the memory address with a reference value; and based on the comparison, enable/restrict actions associated with the program instruction. ### Claim 29 (depends on 28) The controller according to claim 28, wherein the reference value is a memory address of the memory unit delimiting the first area from the second area, and wherein the processing unit is configured to generate an output signal when the received memory address of the instruction is an address of the first area of the memory unit, the output signal being adapted to restrict the actions associated with the instruction of the user firmware. ### Claim 30 (depends on 29) The controller according to claim 29, wherein the output signal of the processing unit is adapted to trigger filtering blocks, the filtering blocks being configured to act on the instructions of the user firmware for preventing the actions associated with the instructions. ### Claim 31 (depends on 28) The controller according to claim 28, wherein the memory unit is a Read Only Memory (ROM) physically separated into the first area and the second area, the first area and the second area being mapped as a continuous address space. ### Claim 32 (depends on 28) The controller according to claim 28, wherein the second area of the memory unit is configured to store a plurality of Application Programming Interfaces (API). ### Claim 33 (depends on 32) The controller according to claim 32, wherein the second area is further configured to store a plurality of Call instructions, each of the Call instructions being associated with a specific memory address of the second area defining a sub-area therein, and wherein each of the Call instructions are adapted to call a respective API of the second area, interfacing the user firmware of the first area with the controller firmware of the second area. ### Claim 34 (depends on 33) The controller according to claim 33, wherein the addresses of the Call instructions stored in the sub-area of the second area are comprised between the addresses of the first area and the remaining addresses of the second area. ### Claim 35 (depends on 32) The controller according to claim 32, comprising a first filtering block configured to mask parameters of the user program instruction for preventing the user program instruction in the first area from directly calling an API stored in the second area. ### Claim 36 (depends on 28) The controller according to claim 28, further comprising a Random Access Memory (RAM) comprising at least a first RAM area directly accessible by the user firmware, and a second RAM area having different RAM addresses from the first RAM area. ### Claim 37 (depends on 36) The controller according to claim 36, comprising a second filtering block configured to prevent the selection of specific address of the second RAM area based on the control signal of the processing unit. ### Claim 38 (depends on 28) The controller according to claim 28, comprising an interface with a plurality of test registers adapted to interface the memory component with a testing machine and/or external controller, each of the test registers being associated with a specific address. ### Claim 39 (depends on 38) The controller according to claim 38, comprising a third filtering block configured to disable the access to specific test registers. ### Claim 40 (depends on 28) The controller according to claim 28, wherein the processing unit is configured to read the address of the program instruction to be executed from a program counter. ### Claim 41 (depends on 28) The controller according to claim 28, wherein the memory component is coupled to a System-on-Chip (SoC) structure. ### Claim 42 (depends on 28) The controller according to claim 28, wherein the processing unit is configured to receive a signal that forces the processing unit to remove all the constraints to the program instructions. ### Claim 43 A memory component, comprising: an array of memory cells; a controller coupled to the array and comprising: a processing unit; and at least one memory unit coupled to the processing unit, the memory unit comprising at least a first area for storing a user firmware and a second area for storing a controller firmware; wherein the processing unit is configured to: receive a memory address of a program instruction to be executed; compare the memory address with a reference value; and based on the comparison, enable/restrict actions associated with the program instructions. ### Claim 44 A method, comprising: storing a user firmware in a first area of a memory unit and storing a controller firmware in a second area of the memory unit; receiving a memory address of a program instruction to be executed; comparing the memory address with a reference value; and based on the comparison, enabling/restricting actions associated with the program instruction. ### Claim 45 (depends on 44) The method according to claim 44, comprising the step of preventing the selection of specific test registers, the specific test registers being adapted to interface the memory component with a testing machine and/or external controller. ### Claim 46 (depends on 44) The method according to claim 44, comprising recognizing different users having different privileges and applying different constraints to the actions associated with the program instruction according to the different privileges. ### Claim 47 (depends on 44) The method according to claim 44, further comprising at least a RAM and a ROM, the ROM being divided into at least a first area and second area, the method comprising: writing a firmware into a portion of the RAM using a JTAG protocol; invoking an API stored in the second area of the ROM; moving, via the API, the firmware to the first area of the ROM.