# US 2021/0333325 A1 · Interface to full and reduced pin jtag devices

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- Number: US 2021/0333325 A1
- Document ID: US20210333325A1
- Status: Published application
- Kind: A1
- Application number: 17/369,556
- Filed: 2021-07-07
- Published: 2021-10-28
- Earliest claimed: 2006-10-18
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20210333325A1

## CPC

- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/2815: {Functional tests, e.g. boundary scans, using the normal I/O contacts (contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00)}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/3025: {Wireless interface with the DUT}
- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

## Claims

### Claim 1

Interface circuitry comprising:
(a) a first port having a first data in pin, a first data out pin, a first clock in pin, and a first mode select in pin;
(b) a second port having a second data out pin coupled to the first data in pin, a second data in pin coupled to the first data out pin, a second clock out pin coupled to the first clock out pin, and a second mode select out pin coupled to the first mode select in pin; and
(c) a third port having a third clock out pin coupled with the first clock in pin, and a third data in and out pin coupled with the first mode select in pin.

### Claim 2 (depends on 1)

The interface circuitry of claim 1 including a full pin interface circuit coupled between the pins of the first port and the pins of the second port, and including a reduced pin interface circuit coupled between the pins of the first port and the pins of the third port.

### Claim 3 (depends on 2)

The interface circuitry of claim 2 in which:
the full pin interface circuit includes a full pin select input;
the reduced pin interface circuit includes a reduced pin select input; and
including shadow protocol circuitry having inputs coupled to the pins of the first port, having a full pin select output coupled to the full pin select input, and having a reduced pin select output coupled to the reduced pin select input.

### Claim 4 (depends on 2)

The interface circuitry of claim 2 in which the full pin interface circuit includes a fourth port having a fourth data out pin coupled to the first data in pin, a fourth data in pin coupled to the first data out pin, a fourth clock out pin coupled to the first clock out pin, and a fourth mode select out pin coupled to the first mode select in pin.

### Claim 5 (depends on 4)

The interface circuitry of claim 4 in which the reduced pin interface circuit includes a fifth clock out pin coupled with the first clock in pin, and a fifth data in and out pin coupled with the first data in pin and with the first data out pin.

### Claim 6 (depends on 1)

The interface circuitry of claim 1 including:
shadow protocol circuitry having inputs coupled to the pins of the first port and having an enable output;
a gate circuit having an input coupled to the enable output, an input coupled to the first mode select in pin, and an output coupled to the second mode select out pin; and
a buffer having an input coupled to the second data in pin, an enable input coupled to the enable output, and a data output coupled to the first data out pin.

### Claim 7

An integrated circuit comprising:
(a) full pin circuitry including a full pin interface, the full pin interface having a data in pin, a data out pin, a clock in pin, and mode select in pin;
(b) reduced pin circuitry including a reduced pin interface, the reduced pin interface having a data in and out pin and a clock in pin; and
(c) a full pin and reduced pin interface circuit including:
a first port of pins having a data in pin, a data out pin, a clock in pin, and a mode select in pin;
a second port of pins coupled to the full pin interface; and
a third port of pins coupled to the reduced pin interface.

### Claim 8 (depends on 7)

The integrated circuit of claim 7 in which the full pin and reduced pin interface circuit includes full pin circuitry coupling the first port of pins to the second port of pins and includes reduced pin circuitry coupling the first port of pins to the third port of pins.

### Claim 9 (depends on 8)

The integrated circuit of claim 8 in which the full pin circuitry has a full pin select input and the reduced pin circuitry has a reduced pin select input, and including shadow protocol circuitry having inputs coupled to the first port of pins, having a full pin select output coupled to the full pin select input, and having a reduced pin select output coupled to the reduced pin select input.

### Claim 10 (depends on 7)

The integrated circuit of claim 7 in which the full pin and reduced pin interface circuit includes full pin interface circuitry coupling the first port of pins to the second port of pins.

### Claim 11 (depends on 7)

The integrated circuit of claim 7 in which the full pin and reduced pin interface circuit includes reduced pin interface circuitry coupling the first port of pins to the third port of pins.

### Claim 12 (depends on 7)

The integrated circuit of claim 7 in which the full pin and reduced pin interface circuit includes:
full pin interface circuitry coupling the first port of pins to the second port of pins, the full pin interface including a full pin select input;
reduced pin interface circuitry coupling the first port of pins to the third port of pins, the reduced pin interface including a reduced pin select input; and
shadow protocol circuitry having inputs coupled to the pins of the first port of pins, having a full pin select output coupled to the full pin select input, and having a reduced pin select output coupled to the reduced pin select input.