# US 2021/0333323 A1 · Improved jtag registers with concurrent inputs

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- Number: US 2021/0333323 A1
- Document ID: US20210333323A1
- Status: Published application
- Kind: A1
- Application number: 16/624,829
- Filed: 2019-05-31
- Published: 2021-10-28
- Earliest claimed: 2019-05-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Antonino Mondello; Alberto Troia
- Web page: https://patentgrep.com/patent/US20210333323A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/1668: {Details of memory controller}
- G11C 29/14: Implementation of control logic, e.g. test mode decoders
- G11C 29/16: using microprogrammed units, e.g. state machines
- G11C 29/32: Serial access; Scan testing
- G11C 2029/3202: {Scan chain}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure relates to an apparatus comprising: a host device or a System-on-Chip: a memory component having an independent structure and including at least an array of memory cells organized in sub-arrays with associated decoding and sensing circuitry; a JTAG interface in said at least an array of memory cells including a boundary-scan architecture; an instruction register in said boundary-scan architecture of the JTAG interface including at least a couple of Bits indicative of the presence of a Test Data Input (TDI) signal. The apparatus has an extended TDI functionality using the data IO to improve the overall performances. A method for improving the communication between a Host or SoC device and an associated independent memory component is also disclosed.

## Claims

### Claim at position 1

-27. (canceled)

### Claim 28

An apparatus, comprising:
a host device or a system-on-chip (SoC);
a memory component having an independent structure and including an array of memory cells, organized in sub arrays, with associated decoding and sensing circuitry;
a joint test action group (JTAG) interface in the array of memory cells including a boundary scan architecture; and
an instruction register in the boundary scan architecture of the JTAG interface including a couple of bits indicative of a presence of a test data input (TDI) signal.

### Claim 29 (depends on 28)

The apparatus of claim 28, wherein the JTAG interfaces comprises a finite state machine (FSM) controlling operation steps of the boundary scan architecture and including the instruction register loaded in a single clock cycle.

### Claim 30 (depends on 29)

The apparatus of claim 29, wherein a data register is configured to be loaded in parallel with the instruction register.

### Claim 31 (depends on 29)

The apparatus of claim 29, wherein a data register containing a predetermined number of bits is configured to be loaded using a data input/out (I/O) capability of a corresponding sub array of the sub arrays.

### Claim 32 (depends on 28)

The apparatus of claim 28, wherein a further couple of bits of the instruction register are indicative of a data register to be selected.

### Claim 33 (depends on 32)

The apparatus of claim 32, wherein the instruction register is configured to contain a flexible TDI for concurrent inputs in JTAG registers.

### Claim 34 (depends on 28)

The apparatus of claim 28, wherein a content of the instructions register is configured to contain a flexible TDI for concurrent inputs in JTAG registers.

### Claim 35

A device, comprising:
a memory component, having an independent structure couplable to a host device or a system-on-ship (SoC), including an array of memory cells organized in sub arrays with associated decoding and sensing circuitry;
a joint test action group (JTAG) interface in the array of memory cells including a boundary scan architecture; and
an instruction register in the boundary scan architecture of the JTAG interface includes a couple of bits indicative of a presence of a test data input (TDI) signal.

### Claim 36 (depends on 35)

The device of claim 35, including:
a plurality of memory blocks in each sub array of the sub arrays; and
a plurality of independently addressable extended pages in each block, each extended page including a group of data, address, and ECC bits.

### Claim 37 (depends on 36)

The device of claim 36, wherein an extended page of the plurality of independently addressable extended pages includes the group of data, address, and ECC bits includes at least 168 bits.

### Claim 38 (depends on 36)

The device of claim 36, wherein an extended page of the plurality of independently addressable extended pages includes the group of data, address, and ECC bits includes at leas 128 data bit, at least 24 address bit, and at least 16 ECC bit.

### Claim 39 (depends on 36)

The device of claim 36, wherein the sensing circuitry associated with each sub array is structured to read an extended page in a single clock cycle to feed a communication bus with a corresponding number of parallel bits working as TDI and depending from the selected registers.

### Claim 40 (depends on 39)

The device of claim 39, wherein four parallel lines are dedicated for the instruction register, eight lines for an address register, and 128 lines for a data register.

### Claim 41 (depends on 35)

The device of claim 35, wherein the JTAG interface comprises a finite state machine (FSM) controlling operation steps of the boundary scan architecture.

### Claim 42 (depends on 41)

The device of claim 41, wherein the instruction register is loaded in a single clock cycle.

### Claim 43 (depends on 35)

The device of claim 35, wherein a further couple of bits of the instruction register are indicative of a data register to be selected.

### Claim 44 (depends on 35)

The device of claim 35, wherein a content of the instruction register is a flexible TDI for concurrent inputs in a JTAG register.

### Claim 45

A method, comprising:
providing a joint test action group (JTAG) finite state machine (FSM) interface or a reduced instruction set computer (RISC) controller in a memory array;
selecting an instruction register in a boundary scan architecture of the JTAG FSM interface or RISC controller; and
loading at least a couple of bits of the instruction register indicative of a presence of a test data input (TDI) signal in a single clock cycle and in parallel with data of memory cells of the memory array.

### Claim 46 (depends on 45)

The method of claim 45, further comprising activating, by a host or system-on-chip (SoC) in communication with the memory array, a ShiftIR command of the JTAG FSM interface to retrieve the TDI signal and obtain:
a number of device in the chain; and
a length of the instruction register of the memory array.

### Claim 47 (depends on 45)

The method of claim 45, further comprising providing the instruction register configured to contain a flexible TDI for concurrent inputs in JTAG registers.