Analog/Digital Converter

An analog-to-digital converter comprising:

• N analog processing blocks Ai, each of the N analog processing blocks Ai corresponding to a respective one of channels CHi, wherein i=1 to N and N is an integer, the channels CHi being acquired by dividing a frequency band corresponding to an analog input signal Sx into N parts, the N analog processing blocks Ai being configured to process analog signals of the channels CHi;
• N digital processing blocks Bi, each of the N digital processing blocks Bi corresponding to a respective one of the channels CHi, the N digital processing blocks Bi being configured to process digital signals of the channels CHi;
• and
• an adder configured to output a digital output signal Sy corresponding to the analog input signal Sx by adding channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the N digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis;
• wherein each analog processing block Aj of the N analog processing blocks Ai includes:
• a frequency converter configured to down-convert the analog input signal Sx according to a cutoff frequency fj-1 of a channel CHj-1;
• and
• a sub A/D converter configured to A/D-convert an analog signal Saj acquired by the frequency converter;
• wherein j=2 to N;
• wherein each digital processing block Bj of the N digital processing blocks Bi includes:
• a multiplier configured to double a signal strength of a first digital signal S1j acquired by the sub A/D converter of the analog processing block Aj;
• a subtractor configured to:
• subtract a third digital signal S3j-1 relating to the channel CHj-1 from a second digital signal S2j acquired by the multiplier;
• and
• output a third digital signal S3j of a corresponding channel CHj;
• and
• a frequency converter configured to up-convert the third digital signal S3j to obtain an up-converted third digital signal S3j and outputs the up-converted third digital signal S3j to the adder as a channel output signal Syj of the corresponding channel CHj;
• wherein an analog processing block A1 of the N analog processing blocks Ai includes a sub A/D converter configured to A/D-convert the analog input signal Sx;
• and
• wherein a digital processing block B1 of the N digital processing blocks Bi outputs a first digital signal S11 acquired by the sub A/D converter of the analog processing block A1 as a third digital signal of a corresponding channel CH1 and also outputs the first digital signal S11 to the adder as a channel output signal Sy1 of the corresponding channel CH1.

An analog-to-digital converter comprising:

• N analog processing blocks Ai, each of the N analog processing blocks Ai corresponding to a respective one of channels CHi, wherein i=1 to N and N is an integer, the channels CHi being acquired by dividing a frequency band corresponding to an analog input signal Sx into N parts, the N analog processing blocks Ai being configured to process analog signals of the channels CHi, wherein each analog processing block Aj of the N analog processing blocks Ai includes:
• a frequency converter configured to down-convert the analog input signal Sx according to a cutoff frequency fj-1 of a channel CHj-1;
• and
• a sub A/D converter configured to A/D-convert an analog signal Saj acquired by the frequency converter, wherein j=2 to N;
• N digital processing blocks Bi, each of the N digital processing blocks Bi corresponding to a respective one of the channels CHi, the N digital processing blocks Bi being configured to process digital signals of the channels CHi;
• and
• an adder configured to output a digital output signal Sy corresponding to the analog input signal Sx by adding channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the N digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis.

A method of operating an analog-to-digital converter, wherein the method comprises:

• acquiring, by the analog-to-digital converter, channels CHi by dividing a frequency band corresponding to an analog input signal Sx into N parts, the analog-to-digital converter comprising N analog processing blocks Ai, each of the N analog processing blocks Ai corresponding to a respective one of the channels CHi, wherein i=1 to N and N is an integer;
• processing, by the N analog processing blocks Ai, analog signals of the channels CHi;
• processing, by N digital processing blocks Bi comprised by the analog-to-digital converter, digital signals of the channels CHi, each of the N digital processing blocks Bi corresponding to a respective one of the channels CHi;
• and
• outputting, by an adder comprised by the analog-to-digital converter, a digital output signal Sy corresponding to the analog input signal Sx by adding channel output signals Syi from the channels CHi, the channel output signals Syi being acquired by the N digital processing blocks Bi, so as to synthesize the channel output signals Syi on a frequency axis;
• wherein each analog processing block Aj of the N analog processing blocks Ai includes:
• a frequency converter configured to down-convert the analog input signal Sx according to a cutoff frequency fj-1 of a channel CHj-1;
• and
• a sub A/D converter configured to A/D-convert an analog signal Saj acquired by the frequency converter;
• wherein j=2 to N;
• wherein each digital processing block Bj of the N digital processing blocks Bi includes:
• a multiplier configured to double a signal strength of a first digital signal S1j acquired by the sub A/D converter of the analog processing block Aj;
• a subtractor configured to:
• subtract a third digital signal S3j-1 relating to the channel CHj-1 from a second digital signal S2j acquired by the multiplier;
• and
• output a third digital signal S3j of a corresponding channel CHj;
• and
• a frequency converter configured to up-convert the third digital signal S3j to obtain an up-converted third digital signal S3j and outputs the up-converted third digital signal S3j to the adder as a channel output signal Syj of the corresponding channel CHj;
• wherein an analog processing block A1 of the N analog processing blocks Ai includes a sub A/D converter configured to A/D-convert, by a sub A/D converter of an analog processing block n the analog input signal Sx;
• and
• wherein a digital processing block B1 of the N digital processing blocks Bi outputs a first digital signal S11 acquired by the sub A/D converter of the analog processing block A1 as a third digital signal of a corresponding channel CH1 and also outputs the first digital signal S11 to the adder as a channel output signal Sy1 of the corresponding channel CH1.