# US 2021/0319829 A1 · Dedicated commands for memory operations

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- Number: US 2021/0319829 A1
- Document ID: US20210319829A1
- Status: Published application
- Kind: A1
- Application number: 16/846,481
- Filed: 2020-04-13
- Published: 2021-10-14
- Earliest claimed: 2020-04-13
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Daniele Balluchi; Paolo Amato; Graziano Mirichigni; Danilo Caraccio; Marco Sforzin; Marco Dallabora
- Web page: https://patentgrep.com/patent/US20210319829A1

## CPC

- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 13/003: {Cell access}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- G11C 2013/0076: {Write operation performed depending on read result}
- G11C 2211/5647: Multilevel memory with bit inversion arrangement
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A method comprising:
receiving a dedicated command to a memory from a controller;
responsive to memory cells in a number of groups of resistance variable memory cells being in a first state and receipt of the dedicated command, writing a user data pattern to a target group of the number of groups without first determining states of the cells in the target group.

### Claim 22 (depends on 21)

The method of claim 21, wherein the user data pattern is comprised of data values corresponding to the first state and data values corresponding to a second state.

### Claim 23 (depends on 21)

The method of claim 21, wherein first state represents a reset state.

### Claim 24 (depends on 21)

The method of claim 21, further comprising only writing portions of the user data pattern having a second state.

### Claim 25 (depends on 21)

The method of claim 21, wherein writing the user data further comprises writing the user data using set signals.

### Claim 26 (depends on 25)

The method of claim 25, further comprising writing the user data using a set signal to a first portion of the target group of resistance variable memory cells.

### Claim 27 (depends on 26)

The method of claim 26, further comprising, responsive to memory cells in the number of groups of resistance variable memory cells being in the first state and receipt of the dedicated command, refraining from applying voltage pulses to a second portion of the target group of resistance variable memory cells.

### Claim 28

An apparatus, comprising:
a memory comprising an array of resistance variable memory cells; and
a controller configured to:
determine that a user data pattern comprises a first quantity of data values corresponding to a second state which is greater than a second quantity of data values corresponding to a first state;
responsive to determining that the first quantity of data values is greater than the second quantity of data values, invert the user data pattern;
responsive to memory cells in a number of groups of the resistance variable memory cells being in the first state and receipt of a dedicated command, write the inverted user data pattern to a target group of the number of groups without first determining states of the cells in the target group.

### Claim 29 (depends on 28)

The apparatus of claim 28, wherein the first state is one of a set state or a reset state and the second state is the other of the set state and the reset state.

### Claim 30 (depends on 28)

The apparatus of claim 28, wherein the controller is configured to receive the user data pattern from a host.

### Claim 31 (depends on 28)

The apparatus of claim 28, wherein the controller configured to invert the user data pattern is further configured to:
store the user data pattern in a buffer;
invert the user data pattern stored in the buffer; and
store the inverted user data pattern in the buffer.

### Claim 32

An apparatus, comprising:
a memory comprising an array of resistance variable memory cells; and
a controller configured to:
write all cells in a number of groups of the resistance variable memory cells to a first state, changing, to the first state, only those cells currently in a second state without use of a first user data pattern; and
after all the cells in the number of groups are in the first state, write, in response to a dedicated command received to the memory from a different controller, a second user data pattern to a target group of the number of groups without first determining the states of the target group.

### Claim 33 (depends on 32)

The apparatus of claim 32, wherein the controller configured to, in association with writing all cells in the number of groups to the first state, apply reset signals to only those cells currently in the second state.

### Claim 34 (depends on 32)

The apparatus of claim 32, wherein the controller configured to, in association with writing the second user data pattern to the target group, apply write signals only to cells that are to be written to the second state.

### Claim 35 (depends on 34)

The apparatus of claim 34, wherein the controller is further configured to apply set signals to only the cells that are to be written to the second state.

### Claim 36 (depends on 32)

The apparatus of claim 32, wherein the controller is further configured to:
determine whether the first user data pattern comprises more data values corresponding to the second data state than the first data state; and
responsive to determining that the host data pattern comprises more data values corresponding to the second data state than the first data state, perform pattern inversion prior to storing the host data pattern in the target group so that data values previously corresponding to the second data state correspond to the first data state and data values previously corresponding to the first data state correspond to the second data state.

### Claim 37 (depends on 36)

The apparatus of claim 36, wherein the controller is further configured to set a flag indicating that the target group stores inverted data.

### Claim 38 (depends on 32)

The apparatus of claim 32, wherein the controller is further configured to store a mask corresponding to the second user data pattern in a buffer in response to the dedicated command before writing the second user data pattern to the target group.

### Claim 39 (depends on 38)

The apparatus of claim 38, wherein the controller is further configured to:
read the buffer; and
apply set signals to cells based on the mask.

### Claim 40 (depends on 32)

The apparatus of claim 32, wherein the controller is further configured to write all cells in the number of groups of the resistance variable memory cells to the first state via a background operation.