Deadlock determination method and semiconductor apparatus

A semiconductor apparatus, comprising:

• a loadport;
• an LL chamber;
• a process chamber;
• an ATR, configured to transport a piece of material between the loadport and the LL chamber and transport at least one piece of material in a single step;
• a VTR, configured to transport the piece of material between the LL chamber and the process chamber and transport at least one piece of material in a single step;
• a deadlock determination device, configured to:
• construct a new WRG, wherein:
• at least one process step that includes a plurality of resources is selected from process steps in a WRG that supports transporting a single piece of material;
• the plurality of resources corresponding to the at least one process step are combined;
• and
• a total capacity of each of the process steps is changed according to a combination result to construct the new WRG that supports transporting a plurality of pieces of material;
• and
• determine a deadlock, whether a piece of material scheduling deadlock occurs being determined based on the new WRG;
• wherein:
• the plurality of resources include apparatuses for performing the process steps;
• and
• the total capacity is a sum of a number of workstations of resources corresponding to each process step.