Overload recovery method in sigma delta modulators

A delta sigma modulator, comprising:

• a first adder;
• an integrator stage coupled to an output of the first adder;
• a reconfigurable local resonator coupled to an output of the integrator stage;
• a second adder coupled the output of the integrator stage and an output of the reconfigurable local resonator;
• an analog-to-digital converter (ADC) coupled to an output of the second adder;
• and
• a digital-to-analog converter (DAC) coupled to an output of the ADC and to a subtractive input of the first adder;
• wherein the reconfigurable local resonator is configured to operate as a local resonator in response to an absence of overload conditions and to operate as a low pass filter in response to overload conditions.

A delta sigma modulator, comprising:

• a first adder;
• an integrator stage coupled to an output of the first adder;
• a reconfigurable local resonator coupled to an output of the integrator stage;
• a second adder coupled the output of the integrator stage and an output of the reconfigurable local resonator;
• an analog-to-digital converter (ADC) coupled to an output of the second adder;
• and a digital-to-analog converter (DAC) coupled to an output of the ADC and to a subtractive input of the first adder;
• wherein the integrator stage is a first integrator stage, and wherein the reconfigurable local resonator comprises:
• a third adder coupled to the output of the first integrator stage;
• a second integrator stage coupled to an output of the third adder;
• and
• a third integrator stage coupled to an output of the second integrator stage, wherein the second adder is further coupled to the input of the second integrator stage and to an output of the third integrator stage, and wherein the third adder is further coupled to the output of the third integrator stage.

A delta sigma modulator, comprising:

• a first adder;
• an integrator stage coupled to an output of the first adder;
• a reconfigurable local resonator coupled to an output of the integrator stage;
• a second adder coupled the output of the integrator stage and an output of the reconfigurable local resonator;
• an analog-to-digital converter (ADC) coupled to an output of the second adder;
• and a digital-to-analog converter (DAC) coupled to an output of the ADC and to a subtractive input of the first adder;
• wherein the integrator stage comprises:
• a switched capacitor network coupled to the output of the first adder;
• an integrator comprising:
• an input coupled to an output of the switched capacitor network, and
• an integrator output comprising the output of the integrator stage;
• and
• a capacitor coupled to the input and the integrator output.

A reconfigurable local resonator, comprising:

• an adder;
• a first integrator stage coupled to an output of the adder;
• a second integrator stage coupled to an output of the first integrator stage;
• a T-shaped cell of capacitors comprising:
• a first capacitor coupled to an input of the first integrator stage;
• a second capacitor coupled to the first capacitor;
• and
• a third capacitor coupled to the first and second capacitors;
• and
• a switching stage coupled to the second capacitor and to an output of the second integrator stage, wherein the output of the second integrator stage is further coupled to a subtractive input of the adder.

A delta sigma modulator, comprising:

• a first adder configured to receive an input signal at an additive input;
• an integrator stage configured to receive an output from the first adder and generate an integrated signal;
• a reconfigurable local resonator configured to receive the integrated signal and generate a resonator output signal;
• a second adder configured to receive the resonator output signal, the integrated signal, and the input signal;
• an analog-to-digital converter (ADC) configured to receive an output from the second adder and generate an output signal;
• and
• a digital-to-analog converter (DAC) configured to receive the output signal and generate a feedback signal, wherein the first adder is further configured to receive the feedback signal at a subtractive input;
• wherein the integrator stage comprises a first integrator stage, and wherein the reconfigurable local resonator comprises:
• a third adder configured to receive the integrated signal;
• a second integrator stage configured to receive an output from the third adder and generate a second integrated signal, wherein the second adder is further configured to receive the second integrated signal;
• and
• a third integrator stage configured to receive the second integrated signal and generate a third integrated signal, wherein the resonator output signal comprises the third integrated signal, and wherein the third adder is further configured to receive the resonator output signal at a subtractive input.

A delta sigma modulator, comprising:

• a first adder configured to receive an input signal at an additive input;
• an integrator stage configured to receive an output from the first adder and generate an integrated signal;
• a reconfigurable local resonator configured to receive the integrated signal and generate a resonator output signal;
• a second adder configured to receive the resonator output signal, the integrated signal, and the input signal;
• an analog-to-digital converter (ADC) configured to receive an output from the second adder and generate an output signal;
• and
• a digital-to-analog converter (DAC) configured to receive the output signal and generate a feedback signal, wherein the first adder is further configured to receive the feedback signal at a subtractive input;
• wherein the integrator stage comprises a first integrator stage, and wherein the reconfigurable local resonator comprises:
• a second integrator stage;
• a third integrator stage coupled to an output of the second integrator stage;
• a T-shaped cell of capacitors comprising:
• a first capacitor coupled to an input of the second integrator stage;
• a second capacitor coupled to the first capacitor;
• and
• a third capacitor coupled to the first and second capacitors;
• and
• a switching stage coupled to the second capacitor and to an output of the third integrator stage, wherein the resonator output signal comprises an output of the third integrator stage.