High-level synthesis (hls) method and apparatus to specify parallelism in computer hardware

A non-transitory computer-readable storage medium, the medium storing a software application that when executed by a computer system will cause the computer system to:

• in response to a command from a client to commence operations for a digital design flow for a digital system,
• receive a multi-threaded software program with at least one C++ thread;
• generate a register-transfer level (RTL) hardware description of the at least one C++ thread;
• and
• automatically infer generation of parallel hardware RTL in response to the received at least one C++ thread.

A computer-implemented method, comprising:

• performing high-level synthesis (HLS) for a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) by
• receiving a multi-threaded software program with at least one C++ thread;
• generating a register-transfer level (RTL) hardware description of the at least one C++ thread;
• and
• automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.