Clock recovery device, an error rate measurement device, a clock recovery method, and an error rate measurement method.

A clock recovery device (10), comprising:

• a signal conversion circuit (20) that sequentially converts a 2n+1 value (n is a natural number) pulse amplitude modulation signal to an NRZ (Non Return to Zero) signal;
• and
• a clock recovery circuit (30) that generates a recovery clock signal from the NRZ signal converted by the signal conversion circuit, wherein
• a lower limit threshold voltage is set between n−1 level voltage and n level voltage of the pulse amplitude modulation signal in the signal conversion circuit,
• an upper limit threshold voltage is set between n level voltage and n+1 level voltage of the pulse amplitude modulation signal in the signal conversion circuit,
• the signal conversion circuit outputs an output voltage corresponding to 0 level of the NRZ signal when the voltage of the pulse amplitude modulation signal is equal to or less than the lower limit threshold voltage,
• the signal conversion circuit outputs an output voltage corresponding to 1 level of the NRZ signal when the voltage of the pulse amplitude modulation signal is equal to or higher than the upper limit threshold voltage,
• the signal conversion circuit preserves the output voltage when the voltage of the pulse amplitude modulation signal is in a dead zone between the lower limit threshold voltage and the upper limit threshold voltage.

A clock recovery method, comprising:

• a signal conversion step (S3) to sequentially convert two consecutive symbols of a 2n+1 value (n is a natural number) pulse amplitude modulation signal to one symbol of an NRZ (Non Return to Zero) signal;
• and
• a clock recovery step (S4) to generate a recovery clock signal from the NRZ signal converted by the signal conversion step, wherein
• the signal conversion step converts the two consecutive symbols to 0, when a second symbol of the two consecutive symbols is n−1 or less,
• the signal conversion step converts the two consecutive symbols to 1, when the second symbol of the two consecutive symbols is n+1 or more,
• the signal conversion step converts the two consecutive symbols to 0, when a first symbol of the two consecutive symbols is n−1 or less and the second symbol is n,
• the signal conversion step converts the two consecutive symbols to 1, when a first symbol of the two consecutive symbols is n+1 or more and the second symbol is n,
• the signal conversion step converts the two consecutive symbols to a conversion result of previous two symbols, when both of the two consecutive symbols are n.

A clock recovery method, comprising:

• a signal conversion step (S3) to sequentially convert a 2n+1 value (n is a natural number) pulse amplitude modulation signal to an NRZ (Non Return to Zero) signal;
• and
• a clock recovery step (S4) to generate a recovery clock signal from the NRZ signal converted by the signal conversion step, wherein
• the clock recovery method further comprises a lower limit threshold voltage setting step (S1) to set up a lower limit threshold voltage between n−1 level voltage and n level voltage of the pulse amplitude modulation signal,
• the clock recovery method further comprises an upper limit threshold voltage setting step (S2) to set up an upper limit threshold voltage between n level voltage and n+1 level voltage of the pulse amplitude modulation signal,
• the signal conversion step outputs an output voltage corresponding to 0 level of the NRZ signal when the voltage of the pulse amplitude modulation signal is equal to or less than the lower limit threshold voltage,
• the signal conversion step outputs an output voltage corresponding to 1 level of the NRZ signal when the voltage of the pulse amplitude modulation signal is equal to or higher than the upper limit threshold voltage,
• the signal conversion step preserves the output voltage when the voltage of the pulse amplitude modulation signal is in a dead zone between the lower limit threshold voltage and the upper limit threshold voltage.