Encoding method and device, decoding method and device, and storage medium
AssigneeZte Corporation
InventorsJin Xu, Jun Xu, Liguang Li
Life of this patent
Estimating the term…
Abstract
Provided are an encoding method and device, a decoding method and device, and a storage medium. The encoding method comprises: encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0≤R1≤1; linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence; and cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.
Claims28
An encoding method comprising:
- encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0≤R1≤1;
- linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence;
- and
- cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.
A decoding method comprising:
- decoding a target bit sequence having a code rate R2 with a low density parity check code LDPC having a code rate R1, to obtain an initial to-be-encoded bit sequence, where 0≤R2≤R1≤1, wherein the target bit sequence is formed by cascading a first bit sequence and a second bit sequence, the first bit sequence is obtained by encoding an initial to-be-encoded bit sequence with a LDPC having a code rate R1, and the second bit sequence is obtained by linearly combining at least two bit sequence segments in the first bit sequence.
An encoding device, comprising:
- a first encoding module configured to encode an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0≤R1≤1;
- a second encoding module configured to linearly combine at least two bit sequence segments in the first bit sequence to obtain a second bit sequence;
- and
- a third encoding module configured to cascade the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.
A decoding device comprising:
- a decoding module configured to decode a target bit sequence having a code rate R2 with a low density parity check code LDPC having a code rate R1, where 0≤R2≤R1≤1, wherein the target bit sequence is formed by cascading a first bit sequence and a second bit sequence, the first bit sequence is obtained by encoding an initial to-be-encoded bit sequence with a LDPC having a code rate R1, and the second bit sequence is obtained by linearly combining at least two bit sequence segments in the first bit sequence.
An encoding device comprising a first processor and a first memory configured to store instructions executable by the first processor, wherein when the instructions are executed by the first processor, the first processor is configured to perform operations of:
- encoding an initial to-be-encoded bit sequence with a low density parity check code LDPC having a code rate R1, to obtain an encoded first bit sequence, where 0≤R1≤1;
- linearly combining at least two bit sequence segments in the first bit sequence to obtain a second bit sequence;
- and
- cascading the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.
A decoding device comprising a second processor and a second memory configured to store instructions executable by the second processor, wherein when the instructions are executed by the second processor, the second processor is configured to perform:
- decoding a target bit sequence having a code rate R2 with a low density parity check code LDPC having a code rate R1, to obtain an initial to-be-encoded bit sequence, where 0≤R2≤R1≤1, wherein the target bit sequence is formed by cascading a first bit sequence and a second bit sequence, the first bit sequence is obtained by encoding an initial to-be-encoded bit sequence with a LDPC having a code rate R1, and the second bit sequence is obtained by linearly combining at least two bit sequence segments in the first bit sequence.
Dependencies are inferred from the claim text.