# US 2021/0280783 A1 · Step height mitigation in resistive random access memory structures

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- Number: US 2021/0280783 A1
- Document ID: US20210280783A1
- Status: Published application
- Kind: A1
- Application number: 17/329,247
- Filed: 2021-05-25
- Published: 2021-09-09
- Earliest claimed: 2019-05-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Ming Wang; Chia-Wei Liu; Jen-Sheng Yang; Wen-Ting Chu; Yu-Wen Liao; Huei-Tzu Wang
- Web page: https://patentgrep.com/patent/US20210280783A1

## CPC

- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.

## Claims

### Claim 1

A method for forming a memory structure, comprising:
forming a first metallization layer on a substrate, wherein the first metallization layer comprises first and second conductive structures;
forming a first dielectric layer, wherein a top surface of the first dielectric layer is substantially coplanar with top surfaces of the first and second conductive structures;
etching a first portion of the first dielectric layer surrounding the first conductive structure, such that the first portion of the first dielectric layer is recessed relative to a second portion of the first dielectric layer surrounding the second conductive structure;
depositing a memory stack on the first portion of the first dielectric layer and on the top surface of the first conductive structure;
patterning the memory stack to form a memory structure that covers the top surface of the first conductive structure;
depositing a second dielectric layer to encapsulate the memory stack; and
forming a second metallization layer on the second dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first portion of the first dielectric layer is recessed relative to the second portion of the first dielectric layer surrounding the second conductive structure by a height substantially equal to or less than that of the first conductive structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein patterning the memory stack comprises:
patterning a top electrode layer of the memory stack so that a width of the patterned top electrode layer is less than that of the first conductive structure; and
forming a spacer on a sidewall surface of the patterned top electrode layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein patterning the memory stack comprises removing portions of the memory stack not deposited on the top surface and sidewall surfaces of the first conductive structure.

### Claim 5 (depends on 1)

The method of claim 1, wherein each of the first and second conductive structures comprises a metal surrounded by a liner material, and wherein a top surface of the liner material is higher than a top surface of the metal.

### Claim 6 (depends on 1)

The method of claim 1, wherein depositing the memory stack comprises:
depositing a bottom electrode layer on sidewall surfaces and the top surfaces of the first and second conductive structures;
depositing a third dielectric layer on the bottom electrode layer; and
depositing a top electrode layer on the third dielectric layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising depositing a capping layer between the third dielectric layer and the top electrode layer.

### Claim 8 (depends on 6)

The method of claim 6, further comprising forming a third conductive structure in contact with a top surface of the top electrode layer.

### Claim 9

A method for forming a memory structure, comprising:
forming first and second conductive structures on a substrate, wherein the first and second conductive structures comprise first and second pairs of sidewall surfaces, respectively;
depositing a dielectric layer on the substrate, wherein first and second portions of the dielectric layer cover the first and second pairs of sidewall surfaces, respectively;
forming a masking layer on the second conductive structure and the second portion of the dielectric layer;
etching the first portion of the dielectric layer such that:
portions of the first pair of sidewall surfaces are exposed; and
the second portion of the dielectric layer is protected by the masking layer; and
forming a memory stack on the exposed portions of the first pair of sidewall surfaces and on a top surface of the first conductive structure.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
etching a top electrode layer of the memory stack to a width less than that of the first conductive structure; and
depositing a spacer material on sidewall surfaces of the etched top electrode layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein forming the memory stack comprises:
depositing a bottom electrode layer;
depositing an other dielectric layer on the bottom electrode layer; and
depositing a top electrode layer on the other dielectric layer.

### Claim 12 (depends on 11)

The method of claim 11, further comprising depositing a capping layer between the other dielectric layer and the top electrode layer.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming a third conductive structure in contact with a top surface of the memory stack.

### Claim 14 (depends on 9)

The method of claim 9, further comprising depositing an other dielectric layer to encapsulate the memory stack by depositing the other dielectric layer on a top surface of the memory stack and on sidewall surfaces of the memory stack.

### Claim 15 (depends on 9)

The method of claim 9, wherein etching the first portion of the dielectric layer comprises recessing the first portion of the dielectric layer relative to the second portion of the dielectric layer by a height substantially equal to or less than that of the first conductive structure.

### Claim 16

A method for forming a memory structure, comprising:
forming first and second conductive structures on a substrate;
depositing a dielectric layer on the substrate;
etching a first portion of the dielectric layer surrounding the first conductive structure, such that the first portion of the dielectric layer is recessed relative to a second portion of the dielectric layer surrounding the second conductive structure;
depositing a memory stack on the first and second portions of the dielectric layer and on the first and second conductive structures; and
patterning the memory stack to form a memory structure that covers a top surface of the first conductive structure.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first portion of the dielectric layer is recessed relative to the second portion of the dielectric layer by a height substantially equal to or less than that of the first conductive structure.

### Claim 18 (depends on 16)

The method of claim 16, wherein depositing the memory stack comprises:
depositing a bottom electrode layer;
depositing an other dielectric layer on the bottom electrode layer; and
depositing a top electrode layer on the other dielectric layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising depositing a capping layer between the other dielectric layer and the top electrode layer.

### Claim 20 (depends on 16)

The method of claim 16, further comprising depositing an other dielectric layer on a top surface of the memory structure and on sidewall surfaces of the memory structure to encapsulate the memory structure.