# US 2021/0280780 A1 · Diffusion barrier layer in programmable metallization cell

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2021/0280780 A1
- Document ID: US20210280780A1
- Status: Published application
- Kind: A1
- Application number: 16/807,600
- Filed: 2020-03-03
- Published: 2021-09-09
- Earliest claimed: 2020-03-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Albert Zhong; Cheng-Yuan Tsai; Hai-Dang Trinh; Shing-Chyang Pan
- Web page: https://patentgrep.com/patent/US20210280780A1

## CPC

- H10N 70/828: {Current flow limiting means within the switching material region, e.g. constrictions}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/041: {Modification of switching materials after formation, e.g. doping (shaping H10N70/061)}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.

## Claims

### Claim 1

A memory device comprising:
a substrate;
a bottom electrode overlying the substrate;
a data storage layer overlying the bottom electrode;
a top electrode overlying the data storage layer, wherein a conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode; and
a diffusion barrier layer disposed between the data storage layer and the top electrode.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the top electrode comprises a diffusive species, wherein the diffusion barrier layer is configured to prevent diffusion of the diffusive species from the top electrode to the data storage layer.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the diffusion barrier layer is substantially free of the diffusive species, and wherein the diffusive species is titanium.

### Claim 4 (depends on 1)

The memory device of claim 1, further comprising:
an active metal layer disposed between the data storage layer and the top electrode, wherein the active metal layer comprises a first conductive material and the top electrode comprises a second conductive material different than the first conductive material.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the diffusion barrier layer is disposed between the data storage layer and the active metal layer.

### Claim 6 (depends on 5)

The memory device of claim 5, further comprising:
an upper diffusion barrier layer disposed between the active metal layer and the top electrode, wherein the upper diffusion barrier layer and the diffusion barrier layer comprise a same material.

### Claim 7 (depends on 4)

The memory device of claim 4, wherein the diffusion barrier layer is disposed between the active metal layer and the top electrode, wherein the active metal layer directly contacts the data storage layer.

### Claim 8 (depends on 1)

The memory device of claim 1, wherein a thickness of the diffusion barrier layer is greater than a thickness of the data storage layer.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein sidewalls of the top electrode, sidewalls of the data storage layer, and sidewalls of the diffusion barrier layer are respectively aligned.

### Claim 10

An integrated chip comprising:
a substrate;
a bottom electrode via overlying the substrate; and
a programmable metallization cell overlying the bottom electrode via, wherein the programmable metallization cell comprises a top electrode, a data storage layer, an active metal layer, and a diffusion barrier layer, wherein the top electrode comprises a diffusive species, wherein the top electrode has a lower reactivity to oxygen than the active metal layer, wherein the active metal layer is disposed between the top electrode and the data storage layer, and wherein the diffusion barrier layer underlies the top electrode and is configured to prevent diffusion of the diffusive species to the data storage layer.

### Claim 11 (depends on 10)

The integrated chip of claim 10, wherein the diffusive species is titanium, wherein the diffusion barrier layer comprises ruthenium, tungsten, or iridium.

### Claim 12 (depends on 10)

The integrated chip of claim 10, wherein a bottom surface of the diffusion barrier layer directly contacts a top surface of the data storage layer, wherein a top surface of the diffusion barrier layer directly contacts a bottom surface of the active metal layer.

### Claim 13 (depends on 10)

The integrated chip of claim 10, wherein a bottom surface of the diffusion barrier layer directly contacts a top surface of the active metal layer, wherein a top surface of the diffusion barrier layer directly contacts a bottom surface of the top electrode.

### Claim 14 (depends on 10)

The integrated chip of claim 10, wherein the active metal layer comprises a first conductive material different than the diffusive species, and wherein the diffusion barrier layer comprises a second conductive material different than the first conductive material and the diffusive species.

### Claim 15 (depends on 10)

The integrated chip of claim 10, wherein the diffusion barrier layer and the active metal layer are respectively substantially free of the diffusive species.

### Claim 16 (depends on 10)

The integrated chip of claim 10, wherein the bottom electrode via is spaced laterally between sidewalls of the programmable metallization cell.

### Claim 17 (depends on 10)

The integrated chip of claim 10, wherein a thickness of the data storage layer is less than a thickness of the diffusion barrier layer, wherein the thickness of the diffusion barrier layer is less than a thickness of the active metal layer.

### Claim 18

A method for forming a memory device, the method comprising:
forming a lower conductive wire over a substrate;
forming a bottom electrode via over the lower conductive wire;
forming a memory cell layer stack over the bottom electrode via, wherein the memory cell layer stack includes a bottom electrode, a data storage layer, a diffusion barrier layer, and a top electrode, wherein the diffusion barrier layer is disposed between the data storage layer and the top electrode, wherein the top electrode comprises a diffusive species, and wherein the diffusion barrier layer is configured to block diffusion of the diffusive species; and
patterning the memory cell layer stack, thereby defining a programmable metallization cell.

### Claim 19 (depends on 18)

The method of claim 18, wherein after performing the patterning process sidewalls of the top electrode, sidewalls of the data storage layer, and sidewalls of the diffusion barrier layer are respectively aligned.

### Claim 20 (depends on 18)

The method of claim 18, further comprising:
performing a baking process on the programmable metallization cell, wherein the baking process reaches a high temperature of about 400 degrees Celsius, wherein the data storage layer is substantially free of the diffusive species after performing the baking process.