# US 2021/0280779 A1 · Phase-change memory cell having a compact structure

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- Number: US 2021/0280779 A1
- Document ID: US20210280779A1
- Status: Published application
- Kind: A1
- Application number: 17/328,917
- Filed: 2021-05-24
- Published: 2021-09-09
- Earliest claimed: 2015-06-23
- Assignees: STMicroelectronics (Crolles 2) SAS; STMicroelectronics (Rousset) SAS
- Applicants: Stmicroelectronics (Crolles 2) SAS; Stmicroelectronics (Rousset) SAS
- Inventors: Philippe BOIVIN; Simon JEANNOT
- Web page: https://patentgrep.com/patent/US20210280779A1

## CPC

- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/061: {Shaping switching materials}
- H10N 70/253: {having three or more electrodes, e.g. transistor-like devices}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

## Claims

### Claim 1

A memory cell, comprising:
a semiconductor substrate;
a first insulating layer covering a surface of the semiconductor substrate;
a semiconductor active layer covering the first insulating layer;
a control gate of a selection transistor, the control gate being on the active layer and having a lateral flank;
a second insulating layer covering the lateral flank of the control gate;
first and second conduction regions of the selection transistor, the first and second conduction regions being in the active layer;
a trench through the active layer, the trench being defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;
a variable-resistance element electrically coupled to first conduction terminal of the selection transistor and including:
a first layer of resistive material covering the first lateral flank of the active layer in the trench, and
a second layer of a variable-resistance material that is in contact with the first layer.

### Claim 2 (depends on 1)

The memory cell according to claim 1, wherein the second layer contacts an upper portion of the first layer, and extends longitudinally in a plane parallel to the surface of the substrate.

### Claim 3 (depends on 2)

The memory cell according to claim 2, comprising a dielectric trench isolation formed under the second layer and in the trench and covering a lateral flank of the first layer.

### Claim 4 (depends on 1)

The memory cell according to claim 1, wherein:
the second insulating layer extends above the control gate;
the first layer extends upwardly from the trench along the second insulating layer and reaches a top surface of the second insulating layer; and
the second layer is positioned above the second insulating layer.

### Claim 5

A memory, comprising:
a plurality of wordlines;
a plurality of bit lines;
a plurality of source lines;
a semiconductor substrate;
a first insulating layer covering a surface of the semiconductor substrate;
a semiconductor active layer covering the first insulating layer;
a first memory cell including:
a control gate of a first selection transistor, the control gate being on the active layer and having a lateral flank;
a second insulating layer covering the lateral flank of the control gate;
first and second conduction regions of the first selection transistor, the first and second conduction regions being in the active layer; and
a variable-resistance element electrically coupled to first conduction region of the first selection transistor and including:
a first layer of resistive material extending in the active layer and contacting the first conduction region, and
a second layer contacting the first layer, wherein second layer is a variable-resistance material.

### Claim 6 (depends on 5)

The memory according to claim 5, wherein the first layer extends in a trench through the active layer, covers a first lateral flank of the active layer, and contacts a first contact portion of the second layer, the memory further comprising a second memory cell that includes a third layer of resistive material extending in the trench, covering a second lateral flank of the active layer, and contacts a second contact portion of the second layer.

### Claim 7 (depends on 6)

The memory according to claim 6, wherein the second memory cell includes a second selection transistor that includes:
a control gate formed on the active layer and having a lateral flank;
a third insulating layer covering the lateral flank of the control gate of the second selection transistor;
first and second conduction regions formed in the active layer, wherein the third layer contacts the first conduction region of the second selection transistor.

### Claim 8 (depends on 7)

The memory according to claim 7, wherein the second conduction terminal of the first selection transistor is shared with a third memory cell of the memory and the second conduction terminal of the second selection transistor is shared with a fourth memory cell of the memory.

### Claim 9 (depends on 6)

The memory according to claim 6, further comprising a dielectric trench isolation formed under the second layer and insulating the first layer from the third layer in the trench.

### Claim 10 (depends on 9)

The memory according to claim 9, wherein the second layer extends longitudinally in a plane parallel to the surface of the substrate and makes contact with upper portions of the first and third layers, the first layer being configured to heat a first contact portion of the second layer and make the first contact portion of the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase, and the third layer being configured to heat a second contact portion of the second layer and make the second contact portion of the second layer change phase between the non-conductive amorphous phase and the conductive crystalline phase.

### Claim 11 (depends on 5)

The memory according to claim 5, wherein the second layer extends longitudinally in a plane parallel to the surface of the substrate and makes contact with an upper portion of the first layer, the first layer being configured to heat a contact portion of the second layer and make the contact portion of the second layer change phase between a non-conductive amorphous phase and a conductive crystalline phase.

### Claim 12 (depends on 5)

The memory cell according to claim 5, wherein:
the second insulating layer extends above the control gate of the first selection transistor;
the first layer extends upwardly from the first conduction region along the second insulating layer and reaches a top surface of the second insulating layer; and
the second layer is positioned on the second insulating layer.

### Claim 13

A memory, comprising:
a semiconductor substrate;
a first insulating layer on the semiconductor substrate;
an active layer of a semiconductor material on the first insulating layer;
a control gate of a first selection transistor on the active layer and having a lateral flank;
a second insulating layer covering the lateral flank of the control gate;
first and second conduction regions of the first selection transistor in the active layer;
a trench in the active layer and defined on a first side by a first lateral flank of the active layer and reaching the first insulating layer;
a heater layer of resistive material in the trench covering the first lateral flank of the active layer; and
a layer of a variable resistance material in contact with the heater layer, electrically coupled to the first conduction terminal, the heater layer of resistive material is configured to heat the layer of the variable resistance material.

### Claim 14 (depends on 13)

The memory of claim 13, wherein the heater layer of resistive material is configured to cause the layer of variable resistance material to change phase between a non-conductive amorphous phase and a conductive crystalline phase.

### Claim 15 (depends on 13)

The memory of claim 13, wherein the layer of variable resistance material contacts an upper portion of the heater layer of resistive material and extends longitudinally in a plane parallel to the surface of the substrate.

### Claim 16 (depends on 15)

The memory of claim 15, further comprising a dielectric trench isolation formed under the heater layer of resistive material and in the trench and covering a lateral flank of the heater layer of resistive material.

### Claim 17 (depends on 13)

The memory of claim 13, wherein:
the second insulating layer extends above the control gate;
the heater layer of resistive material extends upwardly from the trench along the second insulating layer and reaches a top surface of the second insulating layer; and
the layer of variable resistance material is positioned above the second insulating layer.

### Claim 18 (depends on 13)

The memory of claim 13, wherein the layer of resistive material extends in the trench through the active layer and contacts a first contact portion of the second layer.

### Claim 19 (depends on 18)

The memory of claim 18, further comprising a third layer of resistive material extending in the trench, covering a second lateral flank of the active layer, and contacting a second contact portion of the layer of variable resistance material.

### Claim 20 (depends on 19)

The memory of claim 19, further comprising:
a control gate of a second selection transistor on the active layer and having a lateral flank;
a third insulating layer covering the lateral flank of the control gate of the second selection transistor; and
first and second conduction regions of the second selection transistor in the active layer, wherein the third insulating layer contacts the first conduction region of the second selection transistor.